19-0296; Rev 0; 8/94
UA
IT MAN
TION K E
VALUA
E
BL
AVAILA
L
500Msps, 8-Bit ADC with Track/Hold
_______________General Description
The MAX101 ECL-compatible, 500Msps, 8-bit analog-
to-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequen-
cy). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time inter-
leaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101 contains a high-perfor-
mance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.
The innovative design of the internal T/H assures an
exceptionally wide 1.2GHz input bandwidth and aper-
ture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
comparator output design and decoding circuitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
less than 1 error per 10
15
clock cycles. And, unlike
other ADCs that can have errors resulting in false full-
scale or zero-scale outputs, the MAX101 keeps the error
magnitude to less than 1LSB.
The analog input is designed for either differential or
single-ended use with a ±270mV range. Sense pins for
the reference input allow full-scale calibration of the
input range or facilitate ratiometric use.
Phase adjustment is available to adjust the relative
sampling of the converter halves for optimizing convert-
er performance. Input clock phasing is also available
for interleaving several MAX101s for higher effective
sampling rates.
____________________________Features
o
o
o
o
o
o
o
o
o
o
500Msps Conversion Rate
7.0 Effective Bits Typical at 250MHz
1.2GHz Analog Input Bandwidth
Less than ±1/2LSB INL
50Ω Differential or Single-Ended Inputs
±270mV Input Signal Range
Ratiometric Reference Inputs
Dual Latched Output Data Paths
Low Error Rate, Less than 10
-15
Metastable States
84-Pin Ceramic Flat Pack
MAX101
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Signal Processing
High-Energy Physics
Communications
______________Ordering Information
PART
MAX101CFR*
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
84 Ceramic Flat Pack
(with heatsink)
*Contact factory for 84-pin ceramic flat pack without heatsink.
_________________________________________________________Functional Diagram
VA
RT
VA
RTS
VA
RBS
VA
RB
MAX101
8
AIN+
AIN-
TRACK
AND
HOLD
CLK
CLK
FLASH CONVERTER
(8 -BIT)
8
FLASH CONVERTER
(8 -BIT)
L
A
T
C
H
E
S
8
ADATA
STROBE
STROBE
B
U
F
F
E
R
DCLK
DCLK
TRK1
TRK1
PH
ADJ
VB
RT
VB
RTS
VB
RBS
VB
RB
L
A
T
C
H
E
S
8
BDATA
________________________________________________________________
Maxim Integrated Products
1
Call toll free 1-800-998-8800 for free literature.
500Msps, 8-Bit ADC with Track/Hold
MAX101
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
V
CC
...........................................................................0V to +7V
V
EE
.............................................................................-7V to 0V
V
CC
- V
EE
.........................................................................+12V
Analog Input Voltage .............................................................±2V
Reference Voltage (VA
RT
, VB
RT
)...........................-0.3V to +1.5V
Reference Voltage (VA
RB
, VB
RB
) ..........................-1.5V to +0.3V
Clock Input Voltage (V
IH
, V
IL
) .....................................-2.3V to 0V
DIV10 Input Voltage (V
IH
, V
IL
).......................................V
EE
to 0V
Output Current, (I
O
max)
T
J
<100°C .......................................................................14mA
100°C < T
J
<125°C.........................................................12mA
Operating Temperature Range...............................0°C to +70°C
Operating Junction Temperature (Note 2)............0°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+250°C
Note 1:
The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage
may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or
shunt the terminals together.
Note 2:
Typical thermal resistance, junction-to-case R
θJC
= 5°C/W and thermal resistance, junction to ambient (MAX101CFR)
R
θJA
=12°C/W, if 200 lineal ft/min airflow is provided. See
Package Information.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 1.02V, VA
RB
, VB
RB
= -1.02V, T
A
= +25°C, unless otherwise noted.
T
MIN
to T
MAX
= 0°C to +70°C. Note 3)
PARAMETER
ACCURACY
Resolution
Integral Nonlinearity (Note 4)
Differential Nonlinearity
DYNAMIC SPECIFICATIONS
Effective Bits
ENOB
f
CLK
= 500MHz,
V
IN
= 95% full scale
(Note 5)
f
AIN
= 10MHz
f
AIN
= 125MHz
f
AIN
= 250MHz
7.6
7.1
7.0
44.5
500
1.2
270
2
230
-305
-17
1.8
49
0.008
315
-215
32
2.5
51
Bits
INL
DNL
AData, BData
AData, BData,
no missing codes
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
8
±0.50
±0.75
±0.75
±0.85
Bits
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
6.7
Signal-to-Noise Ratio
Maximum Conversion Rate
Analog Input Bandwidth
Aperture Width
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Input Offset Voltage
Least Significant Bit Size
Input Resistance
Input Resistance
Temperature Coefficient
SNR
f
CLK
BW
3dB
t
AW
t
AJ
f
AIN
= 125MHz, f
CLK
= 500MHz,
V
IN
= 95% full scale (Note 6)
(Note 7)
Figure 4
Figure 4
Full scale
Zero scale
AIN+, AIN-, T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
AIN+, AIN-, to GND
AIN+ to AIN-, Table 2,
T
A
= T
MIN
to T
MAX
dB
Msps
GHz
ps
ps
V
IN
V
IO
LSB
R
I
mV
mV
mV
Ω
Ω/°C
2
_______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
ELECTRICAL CHARACTERISTICS (continued)
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 1.02V, VA
RB
, VB
RB
= -1.02V, T
A
= +25°C, unless otherwise noted.
T
MIN
to T
MAX
= 0°C to +70°C. Note 3)
PARAMETER
REFERENCE INPUT
Reference String Resistance
Reference String Resistance
Temperature Coefficient
LOGIC INPUTS
Digital Input Low Voltage
Digital Input High Voltage
Digital Input High Current
Input Bias Current
Clock Input Bias Current
LOGIC OUTPUTS (Note 8)
AData, BData
Digital Output Low Voltage
Digital Output Low Voltage
Digital Output High Voltage
Digital Output Voltage
POWER REQUIREMENTS
Positive Supply Current
Negative Supply Current
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
I
VCC
I
VEE
CMRR
PSRR
V
CC
= 5.0V
V
EE
= -5.2V
V
INCM
= ±0.5V
V
CC
(nom) = ±0.25V
V
EE
(nom) = ±0.25V
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
-935
-975
35
40
40
-750
550
765
1065
1130
-525
mA
mA
dB
dB
V
OH
V
OL
DCLK, DCLK
AData, BData,
DCLK, DCLK
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
-1.95
-1.95
-1.3
-1.4
-1.02
-1.10
275
-1.60
-1.50
-1.00
-0.9
-0.70
-0.60
445
V
mV
V
V
IL
V
IH
I
IH
I
B
I
CLK
CLK, CLK
CLK, CLK
DIV10 = 0V
PH
ADJ
= 0V
CLK, CLK = -0.8V
(no termination)
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
-1.1
1.1
3.1
40
50
-1.50
V
V
mA
µA
µA
SYMBOL
R
REF
VA
RT
to VA
RB
CONDITIONS
MIN
100
0.02
TYP
MAX
175
UNITS
Ω
Ω/°C
MAX101
V
OH
- V
OL
DCLK, DCLK
_______________________________________________________________________________________
3
500Msps, 8-Bit ADC with Track/Hold
MAX101
TIMING CHARACTERISTICS
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 1.02V, VA
RB
, VB
RB
= -1.02V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Clock Pulse Width Low
Clock Pulse Width High
CLK to DCLK
Propagation Delay
DCLK to A/BData
Propagation Delay
Rise Time
Fall Time
Pipeline Delay
(Latency)
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
SYMBOL
t
PWL
t
PWH
t
PD1
t
PD2
t
R
t
F
t
NPD
CLK, CLK
CLK, CLK
DIV10 = 0, Figures 1, 2
DIV10 = 0, Figures 1, 2
20% to 80%
20% to 80%
See Figures 2, 3
and Table 1
DCLK
DATA
DCLK
DATA
Divide-by-1 mode
15
CONDITIONS
MIN
0.9
0.9
1.2
0.7
2.3
1.3
400
850
400
700
15
TYP
MAX
2.5
2.5
3.4
1.8
UNITS
ns
ns
ns
ns
ps
ps
Clock
Cycles
All devices are 100% production tested at +25°C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Deviation from best-fit straight line. See
Integral Nonlinearity
section.
See the
Signal-to-Noise Ratio and Effective Bits
section in the
Detailed Description of Specifications.
SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Clock pulse width minimum requirements t
PWL
and t
PWH
must be observed to achieve stated performance.
Outputs terminated through 100Ω to -2.0V.
__________________________________________Typical Operating Characteristics
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 1.02V, VA
RB
, VB
RB
= -1.02V, T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX101 TOC1
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX101 TOC2
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
0
64
128
OUTPUT CODE
192
0.75
0.50
0.25
DNL (LSBs)
0
-0.25
-0.50
-0.75
INL (LSBs)
256
0
64
128
OUTPUT CODE
192
256
4
_______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 1.02V, VA
RB
, VB
RB
= -1.02V, T
A
= +25°C, unless otherwise noted.)
MAX101
FFT PLOT
(f
AIN
= 251.4462MHz)
MAX101 TOC3
FFT PLOT
(f
AIN
= 10.4462MHz)
-10
-20
-30
-40
(dB)
-50
-60
-70
-80
-90
-100
f
CLK
= 250MHz,
SER = -47.2dB,
NOISE FLOOR = -70.5dB,
SPURIOUS = -61.8dB
MAX101 TOC4
MAX110 TOC6
0
-10
-20
-30
-40
(dB)
-50
-60
-70
-80
-90
-100
0
25
50
f
CLK
= 500MHz,
SER = -44.5dB,
NOISE FLOOR = -67.3dB,
SPURIOUS = -58.2dB
0
75
(MHz)
100
125
0
12.5
25
37.5
(MHz)
50
62.5
EFFECTIVE BITS vs. ANALOG INPUT
FREQUENCY (f
AIN
)
(f
CLK
= 500MHz, V
IN
= 95% FS)
MAX110 TOC5
EFFECTIVE BITS vs. CLOCK
FREQUENCY (f
CLK
)
(f
AIN
= 500MHz, V
IN
= 95% FS)
8
8
EFFECTIVE BITS
7
EFFECTIVE BITS
0
50
100
150
200
f
AIN
(MHz)
250
300
7
6
6
0
100
200
300
400
f
CLK
(MHz)
500
600
_______________________________________________________________________________________
5
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