380B
CY7C1380B
CY7C1382B
512K x 36/1M x 18 Pipelined SRAM
Features
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Fast clock speed: 200, 167, 150, 133 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
Optimal for depth expansion
3.3V (–5% / +10%) power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
isters controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). DQ
a,b,c,d
and DP
a,b,c,d
apply to
CY7C1380B and DQ
a,b
and DP
a,b
apply to CY7C1382B. a, b,
c, d each are 8 bits wide in the case of DQ and 1 bit wide in
the case of DP.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc con-
trols DQc and DPc. BWd controls DQd and DPd. BWa, BWb,
BWc, and BWd can be active only with BWE being LOW. GW
being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1380B and the CY7C1382B
are JEDEC standard JESD8-5 compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1380B and CY7C1382B SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
Selection Guide
200 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
3.0
315
20
167 MHz
3.4
285
20
150 MHz
3.8
265
20
133 MHz
4.2
245
20
Cypress Semiconductor Corporation
Document #: 38-05267 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised October 8, 2001
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