Crystal Clock Oscillator
Technical Data
Frequency Range:
Frequency Stability:
*Aging:
Temperature Range:
Operating:
Storage:
Supply Voltage (V
CC
):
Supply Current:
Output Drive:
ACTUAL SIZE
3.3V, PECL, FR4
SEL481 / SEL482 Series
200 MHz to 670 MHz
±20, ±25, ±50 or ±100 ppm over all conditions: calibration tolerance,
operating temperature, rated input (supply) voltage, load, *aging, shock
and vibration.
30 days (±7ppm in 10 years typical)
0 to +70°C or -40 to +85°C
-55 to +125°C
+3.3V PECL
85mA typ, 110mA max
Description
A crystal controlled, high frequency,
highly stable oscillator, compatible with
LVPECL logic. The output can be disabled
to facilitate testing or combining with mul-
tiple clocks. The oscillator is packaged
in leadless SMD FR4 SO20 available in
four (4) or six (6) pad configurations (see
part number builder) and achieves excep-
tional frequency stability. This oscillator
is ideal for today's automated assembly
environments.
Applications & Features
• SONET/SDH/DWDM linecards
• XGigE NICs
• Optical SOHO FTTC/FTTP OC-12
& STM-4 first/last mile networking
• 3.3V PECL (LVPECL) capability
• Frequency range from 200 to
670MHz
• Disable output feature available
• Economical and rugged FR4 package
• Guaranteed long-term aging avail-
able, consult SaRonix for details
• Designed for standard reflow and
washing techniques
• Available on tape & reel; 16mm tape,
500pcs per reel
• See SEL393x Series for frequencies
≤ 200MHz
• See SEL381x Series for comparable
performance in a smaller ceramic
5x7mm package
• See SDS3811 Series for new LVDS
capability in a smaller ceramic
5x7mm package
Symmetry:
45/55% max @ V
BB
or Complementary Outputs Crossing
Rise & Fall Times:
550ps typ, 850ps max, 20% to 80% of waveform
Logic 0:
≤ V
CC
-1.620V (-40 to 85°C )
Logic 1:
≥ V
CC
-1.025V (0 to +70°C), V
CC
-1.085V (-40 to 85°C)
Load:
50Ω to V
CC
-2V
Accumulated Jitter:
10ps RMS (1-sigma) max, accumulated in 20,000 adjacent periods
Phase Jitter:
3ps RMS (1-sigma) max, in 12kHz to 40MHz Freq. Band
Total Jitter:
50ps peak-to-peak max in 100,000 random periods
Output Enable/Disable for SEL481x (n/a for SEL4810):
Output Enable Voltage:
≤ Level 0 or open
Disable Voltage:
≥ Level 1 (Q & Q outputs disabled to High Impedance)
Output Enable/Disable for SEL482x:
Output Enable:
≥ Level 1 or open
Output Disable:
≤ Level 0 (Q & Q outputs disabled to High Impdeance)
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Resistance to Soldering Heat:
Solvent Resistance:
Environmental:
Thermal Shock:
Moisture Resistance:
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-883, Method 2004, Condition D
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 210, Condition I or J
MIL-STD-202, Method 215
MIL-STD-883, Method 1011, Condition A
MIL-STD-833, Method 1004
Solder Reflow Guide
½½½½½½½½½½½ ½ ½½
½½½
½½½
½½½
½½½½½½ ½½½ ½½½½
½½½½½½½ ½½½
½½½½½½½ ½½½ ½½½½½
½½½½½½½
Output Waveform
½½½½½½½½½½½½½
½½½½½ ½
½½½
½
½½
½½½
½½½½½½½
½½½½½½½½
½½½
½½½½½ ½
½
½½
½½½
½½½½½½½½
½½½ ½½½½ ½½½ ½½½
½½½½½½½ ½½½
½½½½
½ ½ ½ ½½½½½½½
½ ½½½ ½½½
½½ ½½½ ½½½
www.pericom.com
DS-235
REV A
08/02/04
Crystal Clock Oscillator
Technical Data
Package Details
½½½½
½½½½
3.3V, PECL, FR4
SEL481 / SEL482 Series
Part Numbering Guide
SEL48 1 0 B - 312.5000 (T)
Series
SaRonix, LVPECL FR4SO20
½½½
½½½½
1 = 3.3V PECL, Hi-True Disable
2 = 3.3V PECL, Hi-True Enable
Connection Options
Pad: 1 / 2
/
3 /
4
/
5 /
6 /
Packing Method
(T) = Tape & Reel
full reel increments only
Blank = Bulk
Frequency
Stability
AA = ±20 ppm, 0 to +70°C
A = ±25 ppm, 0 to +70°C
B = ±50 ppm, 0 to +70°C
E = ±50 ppm, -40 to +85°C
F = ±100 ppm, -40 to +85°C
½½½
½½½½
½½½ ½
½½½½
½½½½
½½½ ½
½½½½
½½½½
½½½ ½
½½½ ½
½½½½
½½½½
½½½
½½½½
½½½½
½½½½
½½½ ½
*
0 =
OUT
V
EE
V
EE
V
EE
OUT
OUT
OUT N/C
OUT E/D
V
CC
V
CC
V
CC
V
CC
1 = E/D
2= OUT E/D
*Note: Use with SEL481X only
3 = OUT N/C V
EE
½½½ ½
4 = E/D
5 = N/C
N/C V
EE
E/D
V
EE
OUT OUT V
CC
OUT OUT V
CC
½½½ ½½½½½½½½½½
½½½ ½½½½ ½½½½½½½½½ ½½½½½ ½½½ ½½½
½½½½½½½½½½ ½½½½½½½½½½½½½½ ½½½½½½½ ½½½½½½ ½½½½ ½½½ ½½ ½½½
½½½ ½½½½½
½½½½½½½ ½½½½½½½
½½½½½½½
½½ ½½ ½
½½½½½½½
½½½ ½
½½½½½½½½½
½½½
½½½½½½½ ½½ ½½½½½½
½½½½ ½½ ½½½½
½½½½ ½½ ½½½½
Test Circuit*
½½½½½½½½ ½½½½½½ ½½½½½½½½
½½½½ ½½½½½½
½½½
½
½
½
½½½ ½½½½½½½½ ½½½½½
½½½½½½½½½½½ ½½ ½½½
½½½ ½½½½½½½½ ½½½½½
½½½½½½½½½½½ ½½ ½½½
½
½½½½½
½
½½½½½ ½½½½½½½½ ½½ ½½½½½ ½½½ ½½½½
Recommended Land Pattern
½½½½½½½½½½
½½½½½½½½½½½½½½
½½½½½½½½½
½
½
½½
½
½
½½½½
½½½½
½½½½
½½½½
½½½½
½½½
½½½
½½½ ½½½½½½½ ½½½½½½½½
½
½
½
½
½½½
½½½½
½½½½½ ½½½½½½½ ½½½½½ ½½½ ½½½½½½½ ½½½½½½½½½½½½½ ½½½½½ ½½½½ ½½½½½½½½ ½½½ ½½½½½ ½½½½½½½½½½½½½½ ½½ ½½½
½½½½½½½½½ ½½½ ½½½½½½½½½½½½
½½
½½½½½½½½ ½½½½ ½½½½½½½½½ ½½½½½ ½½½½½½ ½½½½½½½½½½ ½½½½½½½½½
½½½½½½ ½½½½ ½½½½½½½½½½½ ½½
½½
½
½½½½½½
*All specfications subject to changes without notice
www.pericom.com
DS-235
REV A
08/02/04
测试/测量
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
