电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

C1812A823M1XAG7210

产品描述Ceramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, BX, -/+15ppm/Cel TC, 0.082uF, 1812,
产品类别无源元件    电容器   
文件大小160KB,共8页
制造商KEMET(基美)
官网地址http://www.kemet.com
下载文档 详细参数 全文预览

C1812A823M1XAG7210概述

Ceramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, BX, -/+15ppm/Cel TC, 0.082uF, 1812,

C1812A823M1XAG7210规格参数

参数名称属性值
是否Rohs认证不符合
Objectid926647387
包装说明, 1812
Reach Compliance Codenot_compliant
ECCN代码EAR99
YTEOL6.5
电容0.082 µF
电容器类型CERAMIC CAPACITOR
介电材料CERAMIC
高度2.03 mm
JESD-609代码e4
长度4.57 mm
多层Yes
负容差20%
端子数量2
最高工作温度125 °C
最低工作温度-55 °C
封装形式SMT
包装方法TR, Plastic, 13 Inch
正容差20%
额定(直流)电压(URdc)100 V
系列C1812(BX,100V)
尺寸代码1812
温度特性代码BX
温度系数15% ppm/°C
端子面层Gold (Au)
宽度3.18 mm

文档预览

下载PDF文档
CERAMIC HIGH RELIABILITY
GENERAL INFORMATION GR900 SERIES
HIGH RELIABILITY — GR900
GR900 capacitors are intended for use in any application where
the chance of failure must be reduced to the lowest possible
level. While any well-made multilayer ceramic capacitor is an
inherently reliable device, GR900 capacitors receive special
attention in all phases of manufacture including:
— Raw Materials Selection
— Special Designs
— Clean Room Production
— Individual Batch Testing
— C-SAM (when applicable)
— Singular Batch Identity is Maintained
— Destructive Physical Analysis
These parts are well worth the added investment in comparison
to the cost of a device or system failure.
Typical applications include:
Medical, Aerospace, Communication Satellites, Radar, Guidance
Systems.
SCREENING AND SAMPLE TESTS
Each batch receives the following testing/inspections:
Preliminary:
1. Destructive Physical Analysis: (DPA) - A sample is pulled from
each lot and examined per EIA-469 and KEMET’s strict internal
void and delamination criteria. Sampling plan is per MIL-PRF-123.
2. C-SAM - May be performed on batches failing to meet the
DPA criteria for removal of marginal product. Not required on
each lot.
Group A
1. Thermal Shock
— Materials used in the construction of mul-
tilayer ceramic capacitors possess various thermal coefficients of
expansion. To assure maximum uniformity, each part is temper-
ature cycled in accordance to MIL-STD-202, Method 107,
Condition A with Step 3 being 125°C. Number of cycles shall be
20 (100% of lot).
2. Voltage Conditioning
— One of the most strenuous environ-
ments for any capacitor is the high temperature/high voltage test.
All units are subject to twice-rated voltage to the units at the max-
imum rated temperature of 125°C for a minimum of 168 hours
and a maximum of 264 hours. The voltage conditioning may be
terminated at any time during 168 hours to 264 hours time inter-
val that confirmed failures meet the requirements of the PDA dur-
ing the last 48 hours of 1 unit or .4% (100% of lot).
Optional Voltage Conditioning (Accelerated Voltage
Conditioning)
— All conditions of the standard voltage condi-
tioning apply with the exception of increased voltage and
decreased test time. Refer to MIL-PRF-123 for the proper formula.
*Step 5 is performed on chips at this point (100% of lot).
3. Dielectric Withstanding Voltage
— 250% of the dc rated volt-
age at 25°C (100% of lot).
4. Insulation Resistance
— The 25°C measurement with rated
voltage applied shall be the lesser of 100 GΩ or 1000 megohm-
microfarads (100% of lot).
*5. Insulation Resistance
— The 125°C measurement with
rated voltage applied shall be the lesser of 10 GΩ or 100
megohm-microfarads (100% of lot). For chips, 125°C IR is per-
formed prior to Step 3 above.
6. Storage
at 150°C for 2 hours minimum without voltage applied
followed by a 12-hour minimum stabilization period (temperature
characteristic BX only).
7. Capacitance
— Shall be within specified tolerance at 25°C
(100% of lot). (Aging phenomenon is taken into account for BX
dielectric to obtain capacitance.)
8. Dissipation Factor
— Shall not exceed 2.5% for X7R (BX)
dielectric, 0.15% for C0G (BP) dielectric at 25°C. (100% of lot.)
9. Percent Defective Allowable (PDA)
— The overall PDA is 8%
for parts outside the MIL-PRF-123 values. The PDA is per MIL-
PRF-123 for all parts that are valid MIL-PRF-123 values. The PD
includes steps 1 through 8 above with the following exceptions.
Capacitance exclusion - capacitance values no more than 5% or
.5pF, whichever is greater for BX characteristic or 1% or .3pF,
whichever is greater for BP characteristic beyond specified toler-
ance limit, shall be removed from the lot but shall not be consid-
ered defective for determination of the PD.
Insulation Resistance at 25°C — Product which is not acceptable
for twice the military limit but is acceptable per the military limit,
is removed from the lot but shall not be considered defective for
determination of the PD.
10. Visual and Mechanical Examination
— Performed per MIL-
PRF-123 criteria.
11. Radiographic Examination (Leaded Devices Only)
Radial devices receive a one-plane X-ray.
12. Destructive Physical Analysis (DPA)
— A sample is exam-
ined on each lot per EIA-469. Sampling Plan is per MIL-PRF-123.
STANDARD PACKAGING
All products are packaged in trays except C512 capacitors which
are packaged 1 piece per bag.
DATA PACKAGE
A data package is sent with each shipment which contains:
1.
Final Destructive Physical Analysis (DPA) report.
2.
Certificate of Compliance stating that the parts meet all applic-
able requirements of the appropriate military specification to the
best failure level to which KEMET is approved.
3.
Summary of Group A Testing.
12
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
SHT31测评+温湿度精度
本帖最后由 sylar^z 于 2020-1-30 17:16 编辑 SHT31是一款新型数字传感器,其温度检测范围0-90℃,精度为±0.2℃,湿度检测范围为0-100%,精度为±2%。 本次测试分两个部 ......
sylar^z 测评中心专版
网友拆解1968年的美国军用电脑
538081 这台机器在本人的eBay收藏夹里呆了很久,某日无意间扫了一眼收藏夹,突然发现卖家大降价,只要15刀,还有best offer选项。15刀你买不了吃亏,15刀你买不了上当。事不宜迟果断下手。 ......
ohahaha 以拆会友
74ls192芯片
怎么解决倒数计时器中的,在倒数计时的过程中不能置数啊,用的是74ls192芯片(置数端11号腿怎么接啊)...
ohshit 综合技术交流
Verilog HDL练习题和Verilog基础知识适合verilog新人.rar
Verilog HDL练习题和Verilog基础知识适合verilog新人Verilog的135个经典设计实例...
493025560 FPGA/CPLD
Altium Designer14版与10版比较(转)
作者:朱长江 Altium Designer 14是Altium公司于2013年10月推出的Altium Designer最新版本。该版本比10版在界面和功能上都有了相当大的改进。笔者作为10版的深度用户,自然很想知道14版相对 ......
qwqwqw2088 PCB设计
高速PCB设计EMI规则探讨(二)
规则五:高速PCB设计的布线方向规则 相邻两层间的走线必须遵循垂直走线的原则,否则会造成线间的串扰,增加EMI辐射,如下图: 此主题相关图片如下: 39515 相邻的布线层遵循横平竖垂的布线 ......
心仪 PCB设计

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 358  2445  2928  109  323  8  50  59  3  7 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved