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IS61QDPB24M18C2-400M3LI: 产品描述QDR SRAM,; 产品类别存储存储; 文件大小756KB，共31页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/; 标准

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IS61QDPB24M18C2-400M3LI概述

QDR SRAM,

IS61QDPB24M18C2-400M3LI规格参数

参数名称	属性值
是否Rohs认证	符合
Objectid	8315636689
包装说明	LBGA,
Reach Compliance Code	compliant
Country Of Origin	Mainland China, Taiwan
ECCN代码	3A991.B.2.A
YTEOL	7.3
最长访问时间	0.45 ns
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	17 mm
内存密度	75497472 bit
内存集成电路类型	QDR SRAM
内存宽度	18
湿度敏感等级	3
功能数量	1
端子数量	165
字数	4194304 words
字数代码	4000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	4MX18
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
座面最大高度	1.4 mm
最大供电电压 (Vsup)	1.89 V
最小供电电压 (Vsup)	1.71 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	10
宽度	15 mm

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IS61QDPB24M18C/C1/C2

IS61QDPB22M36C/C1/C2

4Mx18, 2Mx36

72Mb QUADP (Burst 2) Synchronous SRAM

(2.5 CYCLE READ LATENCY)

FEATURES



2Mx36 and 4Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data

valid window.

Separate independent read and write ports with

concurrent read and write operations.

Max. 450 MHz clock for high bandwidth

Synchronous pipeline read with EARLY write

operation.

Double Data Rate (DDR) interface for read and

write input ports.

2.5 Cycle read latency.

Fixed 2-bit burst for read and write operations.

Two input clocks (K and K#) for address and control

registering at rising edges only.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

Data valid pin (QVLD).

+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

HSTL input and output interface.

Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte Write capability.

Fine ball grid array (FBGA) package option:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x

user-supplied precision resistor.

ODT (On Die Termination) feature is supported

optionally on data input, K/K#, and BW

The end of top mark (C/C1/C2) is to define options.

IS61QDPB22M36C : Don’t care ODT function

and pin connection

IS61QDPB22M36C1 : Option1

IS61QDPB22M36C2 : Option2

Refer to more detail description at page 6 for each

ODT option.

APRIL 2018

DESCRIPTION

The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/

-C2 are 72Mb synchronous, high-performance CMOS static

random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for

high-speed bus turnaround. The rising edge of K clock

initiates the read/write operation, and all internal operations

are self-timed.

Refer to the

description of the basic operations of these

SRAMs.

The input address bus operates at double data rate.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered half a cycle

earlier than the write address. The first data-in burst is

clocked at the same time as the write command signal, and

the second burst is timed to the following rising edge of the

K# clock.

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the second rising

edge of the K# clock (starting two and half cycles later after

read command). The data-outs from the second bursts are

updated with the third rising edge of the K clock. The K and

K# clocks are used to time the data-outs.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interface.

for a



without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

04/23/2018

IS61QDPB24M18C/C1/C2

IS61QDPB22M36C/C1/C2

Ball Description

Symbol

K, K#

Type

Input

Description

Input clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of

phase with K. All synchronous inputs must meet setup and hold times around the clock rising

edges. These balls cannot remain VREF level.

Synchronous echo clock outputs: The edges of these outputs are tightly matched to the

synchronous data outputs and can be used as a data valid indication. These signals are free

running clocks and do not stop when Q tri-states.

DLL disable and reset input: when low, this input causes the DLL to be bypassed and reset the

previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock

time. The device behaves in one clock read latency mode when the DLL is turned off. In this mode,

the device can be operated at a frequency of up to 167 MHz.

Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

CQ#.

Synchronous address inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. These inputs are ignored when device is deselected.

Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K

and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of

individual signals.

The x18 device uses D0~D17. D18~D35 should be treated as NC pin.

The x36 device uses D0~D35.

Synchronous data outputs: Output data is synchronized to the respective CQ and CQ#, or to the

respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.

See BALL CONFIGURATION figures for ball site location of individual signals.

The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.

The x36 device uses Q0~Q35.

Synchronous write: When low, this input causes the address inputs to be registered and a WRITE

cycle to be initiated. This input must meet setup and hold times around the rising edge of K.

Synchronous read: When low, this input causes the address inputs to be registered and a READ

cycle to be initiated. This input must meet setup and hold times around the rising edge of K.

Synchronous byte writes: When low, these inputs cause their respective byte to be registered and

written during WRITE cycles. These signals are sampled on the same edge as the corresponding

data and must meet setup and hold times around the rising edges of K and #K for each of the two

rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffers.

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and

Operating Conditions for range.

Ground of the device

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this

ball to ground. This ball can be connected directly to VDDQ, which enables the minimum

impedance mode. This ball cannot be connected directly to VSS or left unconnected.

In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.

The ODT range is selected by ODT control input.

IEEE1149.1 input pins for JTAG.

IEEE1149.1 output pins for JTAG.

No connect: These signals should be left floating or connected to ground to improve package heat

dissipation.

ODT control; Refer to SRAM features for the details.

CQ, CQ#

Output

Doff#

Input

QVLD

Output

Input

D0 - Dn

Input

Q0 - Qn

Output

Input

reference

Power

Ground

REF

DDQ

Input

TMS, TDI, TCK

TDO

ODT

Input

Output

N/A

Input

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

04/23/2018

IS61QDPB24M18C/C1/C2

IS61QDPB22M36C/C1/C2

The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array

on the third write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read

address followed by the same write address produces the latest write data. The SRAM maintains data coherency.

During a write, the byte writes independently control which byte of any of the four burst addresses is written (see

X18/X36 Write Truth Tables

and

Timing Reference Diagram for Truth Table).

Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM to adjust

its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the

SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee

impedance matching is between 175Ω and 350Ω at V

DDQ

=1.5V. The RQ resistor should be placed less than two inches

away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ must never be

connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in

supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances

value. The final impedance value is achieved within 1024 clock cycles.

Depth Expansion

Separate input and output ports enable easy depth expansion, as each port can be selected and deselected

independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending

read and write transactions are always completed prior to deselecting the corresponding port.

Valid Data Indicator (QVLD)

A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with

the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle

before the final valid read data arrives.

Delay Locked Loop (DLL)

Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to

enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match

the clock frequency. Therefore device can have stable output over the temperature and voltage variation.

DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the

AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL

off mode, the device behaves with one clock cycle latency and a longer access time which is known in DDR-I or legacy

QUAD mode.

The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#

for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is

not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being

reset, it gets locked after 2048 cycles of stable clock.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

04/23/2018

IS61QDPB24M18C2-400M3LI

IS61QDPB24M18C2-400M3LI概述

IS61QDPB24M18C2-400M3LI规格参数

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