Datasheet> 器件分类 > 存储> 存储> IS61QDP2B41M36C2-400M3I

文档预览

IS61QDP2B41M36C2-400M3I: 产品描述QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165; 产品类别存储存储; 文件大小857KB，共33页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/

下载文档详细参数全文预览

IS61QDP2B41M36C2-400M3I概述

QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165

IS61QDP2B41M36C2-400M3I规格参数

参数名称	属性值
Objectid	8087745662
包装说明	LBGA,
Reach Compliance Code	unknown
Country Of Origin	Mainland China, Taiwan
ECCN代码	3A991.B.2.A
YTEOL	7.05
最长访问时间	0.45 ns
JESD-30 代码	R-PBGA-B165
长度	17 mm
内存密度	37748736 bit
内存集成电路类型	QDR SRAM
内存宽度	36
功能数量	1
端子数量	165
字数	1048576 words
字数代码	1000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	1MX36
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
座面最大高度	1.4 mm
最大供电电压 (Vsup)	1.89 V
最小供电电压 (Vsup)	1.71 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
宽度	15 mm

文档预览

下载PDF文档

全文
预览

IS61QDP2B42M18C/C1/C2

IS61QDP2B41M36C/C1/C2

2Mx18, 1Mx36

36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

(2.0 Cycle Read Latency)

FEATURES



1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid

window.

Separate independent read and write ports with

concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and write

input ports.

2.0 cycle read latency.

Fixed 4-bit burst for read and write operations.

Clock stop support.

Two input clocks (K and K#) for address and control

registering at rising edges only.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

Data Valid Pin (QVLD).

+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

HSTL input and output interface.

Registered addresses, write and read controls, byte

writes, data in, and data outputs.

Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x user-

supplied precision resistor.

ODT (On Die Termination) feature is supported

optionally on data input, K/K#, and BW

The end of top mark (C/C1/C2) is to define options.

IS61QDP2B41M36C : Don’t care ODT function

and pin connection

IS61QDP2B41M36C1: Option1

IS61QDP2B41M36C2: Option2

Refer to more detail description at page 6 for each

ODT option.

APRIL 2016

DESCRIPTION

The 36Mb IS61QDP2B41M36C/C1/C2 and IS61QDP2B42M18C/C1/C2

are synchronous, high-performance CMOS static random access

memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed

bus turnaround. The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed. Refer to the

Timing

Reference Diagram for Truth Table

for a description of the basic

operations of these QUADP (Burst of 4) SRAMs.

Read and write addresses are registered on alternating rising edges of

the K clock. Reads and writes are performed in double data rate.

The following are registered internally on the rising edge of the

K clock:



Read/write address



Read enable



Write enable



Byte writes for burst addresses 1 and 3



Data-in for burst addresses 1 and 3

The following are registered on the rising edge of the K# clock:



Byte writes for burst addresses 2 and 4



Data-in for burst addresses 2 and 4

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after the

write address. The first data-in burst is clocked one cycle later

than the write command signal, and the second burst is timed

to the following rising edge of the K# clock. Two full clock

cycles are required to complete a write operation.

During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the third

and fourth rising edges of the K clock (starting 2.0 cycles later

after read command). The data-outs from the second and

fourth bursts are updated with the third and fourth rising edges

of the K# clock where the read command receives at the first

rising edge of K. Two full clock cycles are required to complete

a read operation.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.



without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

IS61QDP2B42M18C/C1/C2

IS61QDP2B41M36C/C1/C2

Ball Description

Symbol

K, K#

Type

Input

Description

Input clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of

phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

These balls cannot remain VREF level.

Synchronous echo clock outputs: The edges of these outputs are tightly matched to the

synchronous data outputs and can be used as a data valid indication. These signals are free running

clocks and do not stop when Q tri-states.

DLL disable and reset input: when low, this input causes the DLL to be bypassed and reset the

previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock

time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the

device can be operated at a frequency of up to 167 MHz.

Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

CQ#.

Synchronous address inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. These inputs are ignored when device is deselected.

Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K

and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of

individual signals.

The x18 device uses D0~D17. D18~D35 should be treated as NC pin.

The x36 device uses D0~D35.

Synchronous data outputs: Output data is synchronized to the respective CQ and CQ#, or to the

respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.

See BALL CONFIGURATION figures for ball site location of individual signals.

The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.

The x36 device uses Q0~Q35.

Synchronous write: When low, this input causes the address inputs to be registered and a WRITE

cycle to be initiated. This input must meet setup and hold times around the rising edge of K.

Synchronous read: When low, this input causes the address inputs to be registered and a READ

cycle to be initiated. This input must meet setup and hold times around the rising edge of K.

Synchronous byte writes: When low, these inputs cause their respective byte to be registered and

written during WRITE cycles. These signals are sampled on the same edge as the corresponding

data and must meet setup and hold times around the rising edges of K and #K for each of the two

rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffers.

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating

Conditions for range.

Ground of the device

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this

ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance

mode. This ball cannot be connected directly to VSS or left unconnected.

In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.

The ODT range is selected by ODT control input.

IEEE1149.1 input pins for JTAG.

IEEE1149.1 output pins for JTAG.

No connect: These signals should be left floating or connected to ground to improve package heat

dissipation.

ODT control; Refer to SRAM features for the details.

CQ, CQ#

Output

Doff#

Input

QVLD

Output

Input

D0 - Dn

Input

Q0 - Qn

Output

Input

reference

Power

Ground

REF

DDQ

Input

TMS, TDI,

TCK

TDO

ODT

Input

Output

N/A

Input

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

IS61QDP2B42M18C/C1/C2

IS61QDP2B41M36C/C1/C2

The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array

on the third write cycle. A read cycle to the last two write addresses produces data from the write buffers. The SRAM

maintains data coherency.

During a write, the byte writes independently control which byte of any of the four burst addresses is written (see

X18/X36 Write Truth Tables

and

Timing Reference Diagram for Truth Table).

Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM to adjust

its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the

SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee

impedance matching is between 175Ω and 350Ω at V

DDQ

=1.5V. The RQ resistor should be placed less than two inches

away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ should not be

connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in

supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances

values. The final impedance value is achieved within 1024 clock cycles.

Depth Expansion

Separate input and output ports enable easy depth expansion, as each port can be selected and deselected

independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending

read and write transactions are always completed prior to deselecting the corresponding port.

Valid Data Indicator (QVLD)

A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with

the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle

before the final valid read data arrives.

Delay Locked Loop (DLL)

Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to

enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match

the clock frequency. Therefore device can have stable output over the temperature and voltage variation.

DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the

AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL

off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy

QUAD mode.

The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#

for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is

not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being

reset, it gets locked after 2048 cycles of stable clock.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

推荐资源

谁玩过RS232，请进: 谁玩过RS232啊，不是一般3根线，DB9，2,3,5三根线就可以吗。现在我的问题是，有两路RS232的数据，想通过一个RS232输出，谁做过相关的设计吗，如何实现那。 232数据1———————— ......; deart148 51单片机

ds1302的断电保护功能怎么用呀: 用1302写的时钟，断电后又是初始界面，电池没起到作用，哪位大神会教教我，万分感谢 ...; 狼牙小帅 51单片机

微波毫米波在战场烟尘中的传播: 摘要:在分析战场烟尘介质特性的基础上,计算了微波!毫米波在战场烟尘中的衰减与相移,并利用粒子跟踪法对战场烟尘引起的衰减进行了计算机模拟.数值模拟与实验结果相一致,说明该方法是行之有效的....; JasonYoo 单片机

菜鸟提问，芯片上的黑胶有什么用: 想自己做个系统，于是今天把我的电子词典拆了，发现有两个芯片被看上去好像黑色膏药的胶封住了，其中一个正是CPU。请问那块黑色膏药是什么啊，我搜索过了，不是那种四四方方的黑胶贴片。然后， ......; zhaozonghui 嵌入式系统

示波器测高频脉冲信号失真解决的方法案例: 有位深圳福田华强北的工程师是专门研发生产屏幕的，需要用示波器测量出苹果平板电脑 ipad 给屏幕上电时的一串脉冲信号，示波器捕捉下来后，他就可以对照着模拟出这段信号。但是这位朋友测了好几 ......; Micsig麦科信测试/测量

DA输出电压精度达不到: 使用的是LTC2668-12的芯片，输出电压范围是+-10V，把它分为1024份，按理讲0~1023中任意一个灰度值都对应不同的电压值，但是当灰度值大于200的时候会出现几个灰度值对应同一个电压值的情况，不过 ......; 有星星的天空 stm32/stm8

澳大利亚政府对电子医疗计划期望过高

　　从7月1日开始，澳大利亚居民就可以通过手机申请或者寄送填写好的申请表格给医保办公室，注册个人管理电子健康系统(PCEHR)。目前该系统的某些功能，如：医务人员将病人信息写入病例等，尚在开发阶段。　　与澳大利亚联邦政府情况不同，新南威尔士州目前已经在本州所属的医院里建立了一个基础电子医疗档案系统，该系统覆盖80%的医院床位信息，包括门诊部和手术室。新南威尔士州超过7.5万名临床医生在使用...[详细]
模拟串口的C语言代码

本程序是模拟串口硬件机制写的，使用时可设一定时中断，时间间隔为1/4波特率，每中断一次调用一次接收函数，每中断4次调用一次发送函数,不过.对单片机来说时钟并须要快.要知道9600的波特率的每个BIT的时间间隔是104us.而单片机中断一次压栈出栈一次的时间是20us左右(标准的51核12M晶体)这样处理时间就要考虑清楚了.呵呵.以下程序是放在定时器中断程序函数内的 //接收部分 sbit ...[详细]
9种简单的数字滤波算法(C语言源程序)

假定从8位AD中读取数据（如果是更高位的AD可定义数据类型为int）,子程序为get_ad(); 1、限副滤波 /* A值可根据实际情况调整 value为有效值，new_value为当前采样值滤波程序返回有效的实际值 */ #define A 10 char value; char filter() { char new_value; new_value = get_ad(...[详细]
遥控门禁(RKE)的设计要求

遥控门禁(RKE)系统已经备受用户的青睐，北美80%以上、欧洲70%以上的新车均安装了RKE系统。除了显而易见的便捷性，RKE用于开启汽车制动装置的技术还具有防盗作用。欧洲汽车生产厂商与保险公司合作，要求购置汽车保险时汽车要安装RKE系统。德国已开始推行这一政策，预计在几年内会扩展到整个欧洲。大多数RKE系统采用单向(单工)通信，但第二代、第三代RKE系统将提供返回到钥匙的逆向通信双工操作...[详细]
利用SHARC 2147x处理器提升便携式连续波多谱勒处理能力

浮点数字信号处理已成为精密技术的一贯需求，航空、工业机器和医疗保健等领域要求较高精度的应用通常都有这个需求。医疗超声设备是目前在用的最复杂的信号处理机器之一，并且逐渐向便携式领域扩展。其面临的挑战在于要在不牺牲系统性能的条件下实现这种密集信号处理。凭借低功耗SHARC 2147x处理器的推出，ADI公司已经完全能够解决提供精密处理同时降低功率预算以实现便携式超声等应用的挑战。本文讨论了便携式...[详细]
基于LabVlEW太阳能路灯充放电监测系统

　　 1引言　　太阳能路灯主要由太阳能光电池组件、蓄电池、充放电控制器、照明灯具四大部分组成。太阳能路灯普及推广的瓶颈已不是技术问题，而是成本问题。要在降低成本的基础上，提高系统的稳定性及发挥最大的效能，就要合理搭配太阳能光电池的输出功率和蓄电池容量及负载功率。为此，仅从理论计算是不够的。因为太阳光光强瞬息万变，充电电流和放电电流都在不断变化，理论计算会带来较大误差。只有采取自动跟踪监测...[详细]
DSP／BIOS在电能质量监测终端中的应用

　　DSP(数字信号处理器)在现今的工程应用中使用越来越频繁。其原因主要有三点：第一，它具有强大的运算能力，能够胜任FFT、数字滤波等各种数字信号处理算法；第二，各大DSP厂商都为自己的产品设计了相关的IDE(集成开发环境)，使得DSP应用程序的开发如虎添翼；第三，具有高性价比，相对于它强大的性能，不高的价格有着绝对的竞争力。　　TI为本公司的DSP设计了集成可视化开发环境CCS(Code...[详细]
Mouser 在其工业应用中心推出楼宇自动化站点

2012年7月11日 – 半导体与电子元器件业顶尖设计工程资源与全球分销商Mouser Electronics, Inc.日前在Mouser.com上发布了新的工业应用培训站点。这个全新的站点旨在帮助设计工程师迅速获得楼宇自动化技术的最新发展和主要趋势，以及配套产品信息。站点分为四个区域：应用、特色产品、文章和资源，Mouser的工业应用培训站点是一个综合性资源，涵盖楼宇自动化的...[详细]
中国电网市场的SoC厂商采用MIPS处理器开发智能电网解决方案

为数字家庭、网络、移动和嵌入式应用提供业界标准处理器架构与内核的领导厂商美普思科技公司 (MIPS Technologies, Inc) 以及中国电能计量芯片市场的领导者杭州万工科技(Vango Technologies Inc.)今天宣布，双方将共同合作为中国快速成长的智能电网市场提供解决方案。万工科技将采用 MIPS 科技广受欢迎的 MIPS32® M14K® 处理器内核，为智能电表和智能电...[详细]
博泰语音云驾驶系统亮相开启智能生活

博泰悦臻携旗下“语音云驾驶系统”iVo－ka，日前亮相上海物联网大会。　　“语音云驾驶系统iVoka”完全颠覆了人与车传统的交互手段，实现了真正实用意义上的智能“人车对话”，涵盖兴趣点搜索与导航、拨打电话、收发短信、音乐播放、资讯搜索等所有的汽车信息交互应用，更加贴合广大车主对于移动互联网时代汽车信息化生活的多种需求。　　这种全新的智能语音人机交互方式，重新定义了“人与车”之间的关...[详细]
联发科受益低端智能机销售成倍增长

北京时间7月10日下午消息，台湾第一大芯片设计厂商联发科预计，今年第三季度其智能手机芯片出货量将出现两位数增长，同时该公司还有望从低端智能手机的需求增长中进一步获益。　　市场主导力量　　联发科设计的芯片控制着智能手机和其他电子设备的功能，是低端智能手机市场的主导力量。售价60美元至700美元的智能手机产品许多都采用联发科的芯片。　　联发科当前市值约为105亿美元左右，上个月收购了竞争对手...[详细]
8位元MCU将死？

在嵌入式软体专家Mike Barr最近撰写的一篇文章中，他预测32位元处理器将最终击败或是完全取代8位元产品。我还记得，1990年时，一位分析师曾斩钉截铁地对我说，8位元已死，不久的将来将会是32位元的天下。 (小编按：Mike Barr的Trends in embedded software design一文，将于本周五刊登在《电子工程专辑》网站，敬请到时前来观看！) ...[详细]
王鲲：微软携手ARM或让英特尔大本营沦陷

最近几年，虽然英特尔仍然在桌面PC领域继续霸主地位，但行业整体的趋势当然毫无疑问集中在移动设备上，ARM强势的推进，不仅让英特尔想要在移动设备领域有所突破成为极其艰难的任务，并且英特尔自身已经开始面临非常严峻的问题。　　毫不夸张的说，英特尔所遇到的困局远比我们看到的要多得多也严重得多，英特尔自己或许已经非常清楚，但如何来应对，恐怕英特尔自己也难找头绪。　　一切从S...[详细]
罗姆开发出实现业界最小的待机电流6μA的车载用LDO稳压器

罗姆开发出实现了业界最小※的待机电流6μA的、耐压达50V的车载用LDO稳压器“BD7xxL2EFJ-C系列”。在车载用LDO稳压器（以下简称“车载用LDO”）领域，罗姆的开发一直领先于业界。此次，通过独创的电路设计，成功开发出待机电流比传统产品低80％的产品。本产品的面世，非常有助于汽车实现更低功耗。本产品于2012年5月份开始出售样品（样品价格：150日元），从2012年9月份开始暂以月...[详细]
iPPea推出新款可支持Android 4.0冰淇林三明治的外接器

为数字家庭、网络、移动和嵌入式应用提供业界标准处理器架构与内核的领导厂商美普思科技公司 (MIPS Technologies, Inc) 以及领先的Android™娱乐与移动设备设计与制造商iPPea公司今天共同宣布，iPPea推出新款可支持Android 4.0冰淇林三明治的外接器（Dongle）产品iPPea TV，可将智能Android体验带到任何一台支持HDMI的数字电视，售价仅为50美...[详细]

器件捷径: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多