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CD4094BKMSR

产品描述4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16
产品类别逻辑    逻辑   
文件大小89KB,共11页
制造商Intersil ( Renesas )
官网地址http://www.intersil.com/cda/home/
下载文档 详细参数 全文预览

CD4094BKMSR概述

4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16

CD4094BKMSR规格参数

参数名称属性值
是否Rohs认证不符合
Objectid1530377479
零件包装代码DFP
包装说明DFP, FL16,.3
针数16
Reach Compliance Codenot_compliant
计数方向RIGHT
系列4000/14000/40000
JESD-30 代码R-CDFP-F16
JESD-609代码e0
逻辑集成电路类型SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup1250000 Hz
位数8
功能数量1
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DFP
封装等效代码FL16,.3
封装形状RECTANGULAR
封装形式FLATPACK
电源5/15 V
传播延迟(tpd)1134 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class V
座面最大高度2.92 mm
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层TIN LEAD
端子形式FLAT
端子节距1.27 mm
端子位置DUAL
总剂量100k Rad(Si) V
触发器类型POSITIVE EDGE
宽度6.73 mm
最小 fmax0.93 MHz

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CD4094BMS
December 1992
CMOS 8-Stage Shift-and-Store
Bus Register
Pinout
CD4094BMS
TOP VIEW
Features
• High Voltage Type (20V Rating)
• 3-State Parallel Outputs for Connection to Common
Bus
• Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading
• Medium Speed Operation - 5MHz at 10V (typ)
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
STROBE 1
DATA 2
CLOCK
Q1
Q2
Q3
Q4
VSS
3
4
5
6
7
8
16 VDD
15 OUTPUT ENABLE
14 Q5
13 Q6
12 Q7
11 Q8
10 Q’S
9 QS
Functional Diagram
SERIAL
OUTPUTS
10 Q’S
8-STAGE
SHIFT
REGISTER
9
QS
Applications
• Serial-to-Parallel Data Conversion
• Remote Control Holding Register
• Dual-Rank Shift, Hold, and Bus Applications
DATA
CLOCK
2
3
Description
CD4094BMS is a 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
is transferred to the storage register when the STROBE input is
high. Data in the storage register appears at the outputs when-
ever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of
CD4094BMS devices. Data is available at the QS serial output
terminal on positive clock edges to allow for high-speed opera-
tion in cascaded systems in which the clock rise time is fast. The
same serial information, available at the Q’S terminal on the next
negative clock edge, provides a means for cascading
CD4094BMS devices when the clock rise time is slow.
The CD4094BMS is supplied in these 16 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
STROBE
1
8-BIT
STORAGE
REGISTER
OUTPUT
ENABLE
15
3-STATE
OUTPUTS
VDD = 16
VSS = 8
PARALLEL OUTPUTS Q1 - Q8
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3194
7-1083

 
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