Metal Package Full Size DIP and Half DIP, TTL / HC-MOS
HCOF/HCOH Series
HCOF Package
20.7
4
3
Product Features:
Low Jitter, Non-PLL Based Output
CMOS/TTL Compatible Logic Levels
Compatible with Leadfree Processing
Applications:
Fibre Channel
Server & Storage
Sonet /SDH
802.11 / Wifi
T1/E1, T3/E3
System Clock
12.6
1
2
7.62
Frequency
Output Level
HC-MOS
TTL
Duty Cycle
Rise / Fall Time
Output Load
Frequency Stability
Start-up Time
Enable / Disable
Time
Supply Voltage
Current
Operating
Storage
Jitter:
RMS(1sigma)
1 MHz-75 MHz
76 MHz-160 MHz
Max Integrated
1 MHz-75 MHz
76 MHz-160 MHz
Max Total Jitter
1 MHz-75 MHz
76 MHz-160 MHz
1 MHz to 160.000 MHz
5.1 Max.
15.24
‘0’ = 0.1 Vcc Max., ‘1’ = 0.9 Vcc Min.
‘0’ = 0.4 VDC Max., ‘1’ = 2.4 VDC Min.
Specify 50% ±10% or ±5% See Table in Part Number Guide
5 nS Max. @ Vcc = +3.3 VDC, 10 nS Max. @ Vcc = +5 VDC ***
Fo < 50 MHz = 10 TTL, Fo > 50 MHz = 5 LSTTL See Table in Part
Number Guide
See Frequency Stability Table (Includes room temperature tolerance and
stability over operating temperature)
10 mS Max.
100 nS Max.
See Input Voltage Table, tolerance ±5 %
40 mA Max. @ 3.3 VDC, 85 mA Max. @ 5.0 VDC ***
See Operating Temperature Table in Part Number Guide
0.36
HCOH Package
12.6
4
3
6 Min.
0.048
12.6
1
2
7.62
7.62
-55
C to +125
C
5.1 Max.
6 Min.
5 pS RMS (1 sigma) Max. accumulated jitter (20K adjacent periods)
3 pS RMS (1 sigma) Max. accumulated jitter (20K adjacent periods)
0.36
0.48
1.5 pS RMS (1 sigma -12KHz to 20MHz)
1 pS RMS (1 sigma -12KHz to 20MHz)
50 pS p-p (100K adjacent periods)
30 pS p-p (100K adjacent periods)
Dimension Units: mm
Pin
1
2
3
4
Connection
Enable / N.C.
GND
Output
Vcc
Part Number Guide
Package
Input
Voltage
5 = 5.0 V
3 = 3.3 V
HCOF -
HCOH -
Sample Part Number:
Operating
Temperature
1 = 0 C to +70 C
6 = -10 C to +70 C
3 = -20 C to +70 C
4 = -30 C to +75 C
2 = -40 C to +85 C
HCOF - 3153BH - 20.000
Output
1 = 10TTL / 15 pF HC-MOS
3 = 15 pF HC-MOS
6 = 30 pF
5 = 50 pF HC-MOS (<40 MHz)
Symmetry
(Duty Cycle)
5 = 45 / 55 Max.
6 = 40 / 60 Max.
Stability
(in ppm)
**E =
10
**D =
15
**F =
20
A =
25
B =
50
C =
100
Enable /
Disable
H = Enable
O = N/C
Frequency
- 20.000 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between Vcc (pin 4) and GND (pin 2) to minimize power supply noise.
* Not available at all frequencies. ** Not available for all temperature ranges. *** Frequency, supply, and load related parameters.
ILSI
America
Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: e-mail@ilsiamerica.com • www.ilsiamerica.com
12/10_A
Specifications subject to change without notice
Page 1
Metal Package Full Size DIP and Half DIP, TTL / HC-MOS
Pb Free Solder Reflow Profile:
HCOF/HCOH Series
Typical Application:
*Units are backward compatible with 240C reflow processes
Package Information:
MSL = N.A. (package does not contain plastic, storage life is
unlimited under normal room conditions).
Termination = e1 (Sn / Cu / Ag over Ni over Kovar base metal).
Environmental Specifications
Thermal Shock
Moisture Resistance
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Hazardous Substance
Solderability
Terminal Strength
Gross Leak
Fine Leak
Solvent Resistance
MIL-STD-883, Method 1011, Condition A
MIL-STD-883, Method 1004
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2007, Condition A
J-STD-020C, Table 5-2 Pb-free devices (except 2 cycles max)
Pb-Free / RoHS / Green Compliant
JESD22-B102-D Method 2 (Preconditioning E)
MIL-STD-883, Method 2004, Test Condition D
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 1014, Condition A2, R1=2x10-8 atm cc/s
MIL-STD-202, Method 215
Marking
Line 1: ILSI and Date Code
Line 2: XXXXXX (Part Number detail = HCOH-XXXXXX-Freq.)
Line 3: Frequency
ILSI
America
Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: e-mail@ilsiamerica.com • www.ilsiamerica.com
12/10_A
Specifications subject to change without notice
Page 2
FPGA/CPLD
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