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RV5C387A
Preliminary
7.Jun.99
I
2
C-Bus Real-Time Clock ICs
with Voltage Monitoring Function
1. OUTLINE
The RV5C387A is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL and SDA, and
configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit
is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month.
The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven
under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time
keeping current is small (TYP. 0.35
µA
at 3 volts). The oscillation halt sensing circuit can be used to judge
the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to
record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32-
kHz clock output function (Nch open-drain output) is intended to output sub-clock pulses for the external
microcomputer. The 32-kHz clock output can be disabled by certain register settings. The oscillation
adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the
oscillation frequency of the crystal oscillator. This model comes in an ultra-compact SSOP10G (Pin Pitch
0.5mm, Height1.2mm, 4.0mm×2.9mm).
2. FEATURES
•
Timekeeping supply voltage ranging from 1.45 to 5.5V
•
Low power consumption
0.35µA TYP (0.8µA MAX) at VDD=3V
•
Only two signal lines (SCL and SDA) required for connection to the CPU.
2
( I C-Bus Interface, 400kHz at VDD≥2.5V, address7bit)
•
Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,
and weeks) (in BCD format)
•
1900/2000 identification bit for Year 2000 compliance
•
Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)
to the CPU and provided with an interrupt flag and an interrupt halt
•
2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and
minute alarm settings)
•
32-kHz clock circuit (N-ch open-drain output)
Designed to disable 32-kHz clock output in response to a command from the host computer.
•
Oscillation halt sensing circuit which can be used to judge the validity of internal data
•
Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
•
Automatic identification of leap years up to the year 2099
•
Selectable 12-hour and 24-hour mode settings
•
Built-in oscillation stabilization capacitors (CG and CD)
•
High precision oscillation adjustment circuit
•
CMOS process
•
Ultra-compact SSOP10G
*) I
2
C-Bus is a trademark of PHILIPS N.V.
Purchase of I2C-Bus components of Ricoh Company, LTD. conveys a license under the Philips I
2
C Patent
Rights to use these components in an I
2
C system, provided that the system comforms to the I
2
C standard
Specification as definded by Philips.
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PRELIMINARY
5. PIN DESCRIPTION
Symbol
SCL
Item
Serial
Clock Line
Serial
Data Line
Interrupt
Output A
Interrupt
Output B
Interrupt
Output C
32kHz Clock
Output
RV5C387A
SDA
/INTRA
/INTRB
/INTRC
32KOUT
OSCIN
OSCOUT
VDD
VSS
Oscillation
Circuit
Input / Output
Positive Power
Supply Input
Negative Power The VSS pin is grounded.
Supply Input
Description
The SCL pin is used to input clock pulses synchronizing the input and output
of data to and from the SDA pin. Allows a maximum input voltage of 5.5
volts regardless of supply voltage.
The SDA pin is used to input or output data intended for writing or reading in
synchronization with the SCL pin. Up to 5.5v beyond VDD may be input.
This pin functions as an Nch open drain output.
The /INTRA pin is used to output periodic interrupt signals to the CPU.
Disabled at power-on from 0 volts. Nch. open drain output.
The /INTRB pin is used to output alarm interrupt (Alarrm_W) signals to the
CPU. Disabled at power-on from 0 volts. Nch. open drain output.
The /INTRC pin is used to output alarm interrupt (Alarm_D) signals to the
CPU. Disabled at power-on from 0 volts. Nch. open drain output.
The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at
power-on from 0 volts. Nch. open drain output. The RV5C387A is designed
to disable 32-kHz clock output in response to a command from the host
computer.
The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal
oscillator (with all other oscillation circuit components built into the
RV5C387A).
The VDD pin is connected to the power supply.
6. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VI
VO
PD
Topt
Tstg
Item
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Pin Name
SCL, SDA
32KOUT, SDA, /INTRA,
/INTRB, /INTRC
Topt = 25°C
Description
-0.3 to +6.5
-0.3 to +6.5
-0.3 to +6.5
300
-40 to +85
-55 to +125
(VSS=0V)
Unit
V
V
V
mW
°C
°C
7. RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
VCLK
fXT
VPUP
Item
Supply Voltage
Timekeeping Voltage
Oscillation Frequency
Pull-up Voltage
Pin Name
(VSS=0V, Topt=-40 to +85°C)
Min,
Typ.
Max.
Unit
2.0
5.5
V
1.45
5.5
V
32.768
kHz
5.5
V
SCL, SDA, /INTRA,
/INTRB, /INTRC
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PRELIMINARY
RV5C387A
9. AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified : VSS=0V,Topt=-40 to +85°C
Input and Output Conditions : VIH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF
Symbol
Item
Condi-
Unit
VDD≥2.0V
VDD≥2.5V
tions
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL Clock Frequency
100
400
KHz
f
SCL
SCL Clock Low Time
4.7
1.3
µs
t
LOW
SCL Clock High Time
4.0
0.6
µs
t
HIGH
4.0
0.6
µs
t
HD;STA
Start Condition Hold Time
4.0
0.6
µs
t
SU;STO
Stop Condition Set Up Time
4.7
0.6
µs
t
SU;STA
Start Condition Set Up Time
250
200
ns
t
SU;DAT
Data Set Up Time
0
0
ns
t
HD;DAT
Data Hold Time
2.0
0.9
µs
t
PL;DAT
SDA “L” Stable Time
After Falling of SCL
2.0
0.9
µs
t
PZ;DAT
SDA off Stable Time
After Falling of SCL
Rising Time of SCL and
1000
300
ns
t
R
SDA (input)
Falling Time of SCL and
300
300
ns
t
F
SDA (input)
Spike Width that can be
50
50
ns
t
SP
removed with Input Filter
S
Sr
P
SCL
t
LOW
t
HIGH
t
HD;STA
t
SP
SDA(IN)
t
HD;STA
t
SU;DAT
t
HD;DAT
t
SU;STA
t
SU;STO
SDA(OUT)
t
PL;DAT
S
Sr
t
PZ;DAT
P
Start Condition
Repeated Start Condition
Stop Condition
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