EN25F10A
EN25F10A
1 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
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Single power supply operation
Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
SPI Compatible: Mode 0 and Mode 3
1 M-bit Serial Flash
1 M-bit/128 K-byte/512 pages
256 bytes per programmable page
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
Dual SPI: CLK, CS#, DQ
0
, DQ
1
, WP#, HOLD#
Quad SPI: CLK, CS#, DQ
0
, DQ
1
, DQ
2
, DQ
3
High performance
104MHz clock rate for Standard SPI
104MHz clock rate for two data bits
104MHz clock rate for four data bits
Low power consumption
10mA typical active current
1
μA
typical power down current
Uniform Sector Architecture:
32 sectors of 4-Kbyte
4 blocks of 32-Kbyte
2 blocks of 64-Kbyte
Any sector or block can be erased individually
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
•
High performance program/erase speed
- Page program time: 0.7ms typical
- Sector erase time: 30ms typical
- 32KB Block erase time 100ms typical
- 64KB Block erase time 200ms typical
- Chip erase time: 0.4 seconds typical
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Lockable 512 byte OTP security sector
•
Support Serial Flash Discoverable
Parameters (SFDP) signature
•
Read Unique ID Number
•
Minimum 100K endurance cycle
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Package Options
- 8 pins SOP 150mil body width
- 8 pins VSOP 150mil body width
- 8 contact USON 2x3 mm
- 8 contact VDFN 5x6 mm
- All Pb-free packages are compliant RoHS,
Halogen-Free and REACH.
•
Industrial temperature Range
GENERAL DESCRIPTION
The EN25F10A is a 1 Megabit (128 K-byte) Serial Flash memory, with enhanced write protection
mechanisms. The EN25F10A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select,
Serial DQ
0
(DI), DQ
1
(DO), DQ
2
(WP#) and DQ
3
(HOLD#). SPI clock frequencies of up to 104MHz are
supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 416MHz
(104MHz x 4) for Quad Output when using the Dual/Quad I/O Fast Read instructions. The memory can
be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The EN25F10A is designed to allow either single
Sector/Block
at a time or full chip erase operation. The
EN25F10A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector
or block
.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
1
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/12
www.eonssi.com
EN25F10A
Figure.1 CONNECTION DIAGRAMS
CS#
DO (DQ
1
)
WP# (DQ
2
)
VSS
1
2
3
4
8
7
6
5
VCC
HOLD# (DQ
3
)
CLK
DI (DQ
0
)
8 - LEAD SOP / VSOP
CS#
DO (DQ
1
)
WP# (DQ
2
)
VSS
1
2
3
4
8
7
6
5
VCC
HOLD# (DQ
3
)
CLK
DI (DQ
0
)
8 - LEAD USON / VDFN
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
2
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/12
www.eonssi.com
EN25F10A
Figure 2. BLOCK DIAGRAM
Address
Buffer
And
Latches
X-Decoder
Flash
Memory
Y-Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CS#
CLK
DI (DQ0)
DO (DQ1)
WP# (DQ2)
HOLD# (DQ3)
Note:
1. DQ
0
and DQ
1
are used for Dual and Quad instructions.
2. DQ
0
~ DQ
3
are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
3
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/12
www.eonssi.com
EN25F10A
Table 1. Pin Names
Symbol
CLK
DI (DQ
0
)
DO (DQ
1
)
CS#
WP# (DQ
2
)
HOLD# (DQ
3
)
Vcc
Vss
NC
Pin Name
Serial Clock Input
Serial Data Input (Data Input Output 0)
*1
*1
Serial Data Output (Data Input Output 1)
Chip
Select
Write Protect (Data Input Output 2)
HOLD# pin (Data Input Output 3)
Supply Voltage (2.7-3.6V)
Ground
No Connect
*2
*2
Note:
1. DQ
0
and DQ
1
are used for Dual and Quad instructions.
2. DQ
2
~ DQ
3
are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ
0
, DQ
1
, DQ
2
, DQ
3
)
The EN25F10A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ
0
, DQ
1
, DQ
2
and DQ
3
) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ
3
) for Quad I/O operation.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ
2
) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
4
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/12
www.eonssi.com
EN25F10A
MEMORY ORGANIZATION
The memory is organized as:
131,072 bytes
Uniform Sector Architecture
4 blocks of 32-Kbyte
2 blocks of 64-Kbyte
32 sectors of 4-Kbyte
512 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
5
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/12
www.eonssi.com
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