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EN25F10-100VIP: 产品描述Flash, 128KX8, PDSO8; 产品类别存储存储; 文件大小426KB，共31页; 制造商Eon; 官网地址http://www.essi.com.tw/; 标准

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EN25F10-100VIP概述

Flash, 128KX8, PDSO8

EN25F10-100VIP规格参数

参数名称	属性值
是否Rohs认证	符合
Objectid	109398734
包装说明	SON, SOLCC8,.25
Reach Compliance Code	unknown
ECCN代码	EAR99
最大时钟频率 (fCLK)	100 MHz
耐久性	100000 Write/Erase Cycles
JESD-30 代码	R-PDSO-N8
内存密度	1048576 bit
内存集成电路类型	FLASH
内存宽度	8
端子数量	8
字数	131072 words
字数代码	128000
最高工作温度	85 °C
最低工作温度	-40 °C
组织	128KX8
封装主体材料	PLASTIC/EPOXY
封装代码	SON
封装等效代码	SOLCC8,.25
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
并行/串行	SERIAL
电源	3/3.3 V
认证状态	Not Qualified
串行总线类型	SPI
最大待机电流	0.000005 A
最大压摆率	0.025 mA
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	NO LEAD
端子节距	1.27 mm
端子位置	DUAL
类型	NOR TYPE
写保护	HARDWARE/SOFTWARE

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EN25F10

1 Megabit Serial Flash Memory with 4Kbytes Uniform Sector

FEATURES

•

Single power supply operation

- Full voltage range: 2.7-3.6 volt

•

1 Mbit Serial Flash

- 1 M-bit/128 K-byte/512 pages

- 256 bytes per programmable page

•

High performance

- 100MHz clock rate

•

Low power consumption

- 5 mA typical active current

- 1

μA

typical power down current

•

Uniform Sector Architecture:

32 sectors of 4-Kbyte

4 blocks of 32-Kbyte

Any sector or block can be

erased individually

•

Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

•

High performance program/erase speed

Page program time: 1.5ms typical

Sector erase time: 150ms typical

Block erase time 800ms typical

Chip erase time: 2 Seconds typical

•

Lockable 256 byte OTP security sector

•

Minimum 100K endurance cycle

•

Package Options

8 pins SOP 150mil body width

8 contact VDFN

All Pb-free packages are RoHS compliant

•

Industrial temperature Range

GENERAL DESCRIPTION

The EN25F10 is a 1M-bit (128K-byte) Serial Flash memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to

256 bytes at a time, using the Page Program instruction.

The EN25F10 is designed to allow either single Sector at a time or full chip erase operation. The

EN25F10 can be configured to protect part of the memory as the software protected mode. The

device can sustain a minimum of 100K program/erase cycles on each sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

EN25F10

SIGNAL DESCRIPTION

Serial Data Input (DI)

The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be

serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)

input pin.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from

(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device

is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the

devices power consumption will be at standby levels unless an internal erase, program or status

consumption will increase to active levels and instructions can be written to and data read from the

device. After power-up, CS# must transition from high to low before a new instruction will be

accepted.

Hold (HOLD#)

The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought

low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will

be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same

SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2) bits and Status Register

Protect (SRP) bits, a portion or the entire memory array can be hardware protected.

Table 1. PIN Names

Symbol

CLK

CS#

WP#

HOLD#

Vcc

Vss

Pin Name

Serial Clock Input

Serial Data Input

Serial Data Output

Chip Enable

Write Protect

Hold Input

Supply Voltage (2.7-3.6V)

Ground

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

EN25F10

OPERATING FEATURES

SPI Modes

The EN25F10 is accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus

operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus

master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal

is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is

sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge

of CLK.

Figure 3. SPI Modes

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the

internal Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on

the same page of memory.

Sector Erase, Block Erase and Chip Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied,

the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a

time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE)

instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an

internal Erase cycle (of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write

Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE

or CE ) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The

Write In Progress (WIP) bit is provided in the Status Register so that the application program can

monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle

is complete.

Active Power, Stand-by Power and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip

Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all

internal cycles have completed (Program, Erase, Write Status Register). The device then goes into

the Stand-by Power mode. The device consumption drops to I

CC1

The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device consumption drops further to I

CC2

. The device re-

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

EN25F10-100VIP

EN25F10-100VIP概述

EN25F10-100VIP规格参数

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