IXD5127
Voltage Detector with Delay Circuit and Manual Reset
FEATURES
o
o
Accuracy ± 0.8%
Low Power Consumption
0.6
µA
(Detect at V
DF
= 1.8 V, V
IN
= 1.62 V)
0.7 µA (Release at V
DF
= 1.8 V, V
IN
= 1.98 V)
Detect Voltage Range 1.5 V – 5.5 V in 0.1 V
increments
Operating Voltage Range 0.7 V – 6.0 V
0
Detect Voltage Temperature Drift ±50 ppm/ C
Output Configuration CMOS (Version C) or N-
channel Open Drain (N Version)
Preprogrammed Release Delay Time
Manual Reset Input
Active High or Active Low Reset Output
0
Operating Ambient Temperature - 40 + 85 C
Packages : USPN-4, SSOT-24, and SOT-25
EU RoHS Compliant, Pb Free
DESCRIPTION
The IXD5127 are highly precise, low power
consumption, CMOS voltage detectors, with manual
reset input and build-in delay circuit manufactured
using laser trimming technology.
It maintains high accuracy, low power consumption,
and accurate release delay time over the full
operation temperature range.
Manual reset input allows IXD5127 generate reset at
any desirable moment.
With low power consumption and high accuracy, the
series is suitable for precision mobile equipment.
The IXD5127 in ultra small packages are ideally
suited for high-density PC boards.
The IXD5127 is available in both CMOS and
N-channel open drain output configurations
Detector is available in USPN-4, SSOT-24, and
SOT-25 packages.
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APPLICATIONS
o
o
o
o
o
Microprocessor reset circuitry
Memory battery back-up circuits
Power-on reset circuits
Power failure detection
System battery life and charge voltage monitors
TYPICAL APPLICATION CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTIC
Release Delay Time vs. Ambient Temperature
IXD5127x27Bx
V
IN
= V
DFL
x 0.9
→V
DFL
x 1.1,
MR
- Open
Pull-up Resistor R
PL
used with N-channel output configuaration only
© 2014 IXYS Corp.
Characteristics subject to change without notice
1
Doc. No. IXD5127_DS, Rev. N0
IXD5127
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input Voltage
MR
Input Voltage
Output Current
CMOS Output
Output
Voltage
N-channel Open Drain
USPN-4
Power Dissipation
SOT-25
SSOT-24
Operating Temperature Range
Storage Temperature Range
All voltages are in respect to V
SS
SYMBOL
V
IN
V
MR
I
OUT
V
RST
P
D
T
OPR
T
STG
RATINGS
– 0.3 ~ +6.5
– 0.3 ~ +6.5
20
– 0.3 ~ V
IN
+ 0.3
≤
6.5
– 0.3 ~ +6.5
100
250
150
– 40 ~ + 85
– 55 ~ +125
UNITS
V
V
mA
V
mW
0
0
C
C
ELECTRICAL OPERATING CHARACTERISTICS
For N-channel open drain configuration R
PULL
= 100 kΩ, V
PULL
= V
IN
PARAMETER
Operating Voltage
Detect Voltage
Hysteresis Width
Supply Current1
3)
Ta = 25
0
C
MIN.
0.7
2)
SYMBOL
V
IN
V
DF
V
HYS
I
SS1
V
DF(T)
1)
CONDITIONS
= 1.5 – 5.5 V,
MR
- Open
V
IN
= 1.0 – 6.0 V
TYP.
E-1
3)
V
DFL
x
0.05
0.6
0.7
1.0
0.7
0.8
1.1
± 50
MAX.
6.0
V
DFL
x
0.08
1.4
1.6
1.9
1.6
1.9
2.35
UNIT
V
V
V
µA
CIRCUIT
V
DFL
x
0.02
V
IN
= V
DFL
x 0.9,
MR
- Open
V
IN
= V
DF
x 1.1
4)
MR
- Open
V
IN
= 1.5 – 1.8 V,
V
IN
= 1.9 – 3.0 V
V
IN
= 3.1 – 5.5 V
V
IN
= 1.5 – 1.8 V,
V
IN
= 1.9 – 3.0 V
V
IN
= 3.1 – 5.5 V
Supply Current2
3)
Detect Voltage
Temperature
Characteristics
Detect Delay Time
6)
Release Delay Time
7)
MR
LOW Level Voltage
MR
HIGH Level Voltage
MR
Pull-up Resistance
MR
Pulse Width
I
SS2
∆
∆
t
DF
t
DR
V
MRL
V
MRH
R
MR
T
MR
µA
- 40
0
C
≤
T
OPR
≤
85
0
C
V
IN
= V
DFL
x 1.1
→
V
DFL
x 0.9,
MR
- Open
V
IN
= V
DFL
x 0.9
→
V
DFL
x 1.1,
MR
- Open
V
DFL
x 1.1
≤
V
IN
≤
6.0 V
V
DFL
x 1.1
≤
V
IN
≤
6.0 V
V
IN
= 6.0 V
V
IN
= 0.7 V
V
IN
= 1.0 V
V
RST
= 0.5 V,
V
IN
= 2.0 V, V
DF(T)
> 2.0 V
MR
- Open
V
IN
= 3.0 V, V
DF(T)
> 3.0 V
N-channel MOSFET
V
IN
= 4.0 V, V
DF(T)
> 4.0 V
V
IN
= 5.0 V, V
DF(T)
> 5.0 V
V
IN
= 6.0V, V
RST
= 5.5 V,
MR
- Open
V
IN
= 6.0 V
P-channel MOSFET
V
IN
= V
DFL
x 0.9, V
RST
= 0 V,
IXD5127CxxA - E
(P-channel)
MR
- Open
V
IN
= V
RST
= 6.0 V,
IXD5127NxxA - E
(N-channel)
MR
- Open
V
IN
= 1.65 V, V
DF(T)
= 1.5 V
V
IN
= 2.0 V, V
DF(T)
≤
1.8 V
V
RST
= 0.5 V,
V
IN
= 3.0 V, V
DF(T)
≤
2.7 V
MR
- Open
V
IN
= 4.0 V, V
DF(T)
≤
3.6 V
N-channel MOSFET
V
IN
= 5.0 V, V
DF(T)
≤
4.6 V
V
IN
= 6.0 V
V
IN
= 0.7 V
V
IN
= 1.0 V
V
IN
= 6.0V, V
RST
= 5.5
V
IN
= 2.0 V, V
DF(T)
> 2.0 V
V,
MR
- Open
V
IN
= 3.0 V, V
DF(T)
> 2.0 V
P-channel MOSFET
V
IN
= 4.0 V, V
DF(T)
> 2.0 V
V
IN
= 5.0 V, V
DF(T)
> 2.0 V
ppm/
0
C
100
9)
µs
ms
V
V
MΩ
ns
E-2
8)
0
1.0
0.4
150
0.014
0.5
4.4
7.0
8.5
9.0
0.3
6.0
3.0
0.8
0.2
1.6
7.0
9.0
11.0
12.0
-4.5
-0.01
RESET
Output Current
IXD5118xxxA – E
versions only
I
OUT1
mA
I
OUT25)
RESET
Leakage Current
IXD5118xxxA – E
versions only
-3.0
mA
I
LEAK
µA
0.01
0.5
4.4
7.0
8.5
9.0
9.0
1.6
7.0
9.0
11.0
12.0
12.0
-0.07
-0.4
-2.0
-3.0
-4.0
-4.5
0.15
I
OUT1
RESET
Output Current
IXD5118xxxF – K
versions only
I
OUT25)
mA
-0.01
-0.9
-1.3
-1.8
-2.5
-3.0
mA
© 2014 IXYS Corp.
Characteristics subject to change without notice
2
Doc. No. IXD5127_DS, Rev. N0
IXD5127
ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED)
Ta = 25
0
C
PARAMETER
RESET
Leakage Current
IXD5118xxxF – K
versions only
NOTE:
1)
2)
V
DF(T
) is a nominal detect voltage
Minimum voltage, at which V
RST
remains below 0.3 V for
IXD5127xxxA – E versions or above 0.4 V for
IXD5127xxxF - K versions
Please refer to the table named Voltage Chart
V
IN
= 6.0 V at V
DF(T)
= 5.5 V
IXD5127C version only
6)
7)
8)
9)
A time between V
IN
= V
DFL
and V
RST
= V
DFL
× 0.45 when
V
IN
falls.
A time between V
IN
=V
DFL
+V
HYS
and V
RST
=V
DFL
× 0.55
when V
IN
rises.
Please refer to the table named Release Delay Time
200 µs for IXD5127NxxF – K versions
SYMBOL
I
LEAK
CONDITIONS
IXD5127CxxA - E
(P-channel)
IXD5127NxxA - E
(N-channel)
V
IN
= V
DFL
x 0.9, V
RST
= 0 V,
MR
- Open
V
IN
= V
RST
= 6.0 V,
MR
- Open
MIN.
TYP.
0.01
-0.01
MAX.
0.15
µA
UNIT
CIRCUIT
3)
4)
5)
Voltage Chart
NOMINAL
DETECT
VOLTAGE
(V)
V
DF(T)
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
DETECT VOLTAGE
(V)
E-1
V
DFL
or V
DFH
MIN.
MAX
1.4880
1.5120
1.5872
1.6128
1.6864
1.7136
1.7856
1.8144
1.8848
1.9152
1.9840
2.0160
2.0832
2.1168
2.1824
2.2176
2.2816
2.3184
2.3808
2.4192
2.4800
2.5200
2.5792
2.6208
2.6784
2.7216
2.7776
2.8224
2.8768
2.9232
2.9760
3.0240
3.0752
3.1248
3.1744
3.2256
3.2736
3.3264
3.3728
3.4272
3.4720
3.5280
NOMINAL
DETECT
VOLTAGE
(V)
V
DF(T)
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
5.30
5.40
5.50
DETECT VOLTAGE
(V)
E-1
V
DFL
or V
DFH
MIN.
MAX.
3.5712
3.6288
3.6704
3.7296
3.7696
3.8304
3.8688
3.9312
3.9680
4.0320
4.0672
4.1328
4.1664
4.2336
4.2656
4.3344
4.3648
4.4352
4.4640
4.5360
4.5632
4.6368
4.6624
4.7376
4.7616
4.8384
4.8608
4.9392
4.9600
5.0400
5.0592
5.1408
5.1584
5.2416
5.2576
5.3424
5.3568
5.4432
5.4560
5.5440
Release Delay Time
TYPE
IXD5127CxxA/IXD5127NxxA
IXD5127CxxB/IXD5127NxxB
IXD5127CxxC/IXD5127NxxC
IXD5127CxxD/IXD5127NxxD
IXD5127CxxE/IXD5127NxxE
IXD5127CxxF/IXD5127NxxF
IXD5127CxxG/IXD5127NxxG
IXD5127CxxH/IXD5127NxxH
IXD5127CxxJ/IXD5127NxxJ
IXD5127CxxK/IXD5127NxxK
RELEASE DELAY TIME
(ms) E-2
t
DR
MIN.
TYP.
MAX.
42.5
50
57.5
85
100
115
170
200
230
340
400
460
680
800
920
42.5
50
57.5
85
100
115
170
200
230
340
400
460
680
800
920
© 2014 IXYS Corp.
Characteristics subject to change without notice
3
Doc. No. IXD5127_DS, Rev. N0
IXD5127
PIN CONFIGURATION
USPN-4
(BOTTOM VIEW)
SSOT-24
(TOP VIEW)
SOT-25
(TOP VIEW)
PIN ASSIGNMENT
USPN-4
1
2
3
4
NOTE
1)
2)
PIN NUMBER
SSOT-24
4
3
2
1
SOT-25
4
1
2
5
3
PIN NAME
RESET
/RESET
MR
V
SS
V
IN
NC
FUNCTIONS
Output Voltage (RESET Active “LOW”
1)
, RESET – Active “HIGH”
2)
)
Manual Reset Input (“HIGH” or “OPEN” State – Normal Operations, “LOW” –
Forced Reset
Ground
Power Input
No internal Connect
Type IXD5127xxxA – E versions
Type IXD5127xxxF – K versions
BLOCK DIAGRAMS
XD5127CxxA - E
IXD5127NxxA - E
IXD5127CxxF - K
IXD5127NxxF – K
Diodes inside the circuits are ESD protection diodes and parasitic diodes.
© 2014 IXYS Corp.
Characteristics subject to change without notice
4
Doc. No. IXD5127_DS, Rev. N0
IXD5127
BASIC OPERATION
The timing diagram shown below exlains operation of the IXD5127xxxA - E in a typical application circuit.
At the initial state, an input voltage V
IN
is higher than the detect voltage V
DFL
, and output voltage V
RST
is equal to
the input voltage V
IN
. In the case of N-channel open drain architecture, the
RESET
pin is in a high-impedance state,
and the output voltage V
RST
is equal to the pull-up voltage.
,
After the elapse of the Detect Delay Time t
DF
that starts when the input voltage V
IN
falls below the detect
voltage V
DFL
, an output voltage V
RST
becomes equal to the ground voltage V
SS
(detection state).
If the input voltage V
IN
drops below minimum operating voltage of 0.7 V, the output goes into undefined state. In
case of N-channel open drain output architecture, an output voltage V
RST
may be equal to the pull-up voltage.
If input voltage V
IN
is above minimum operating voltage of 0.7 V, but less than the release voltage V
DR
, the
output voltage V
RST
is at the ground level.
The delay circuit keeps the output voltage V
RST
at the ground level until the Release Delay Time t
DR
from the
moment, when the input voltage V
IN
becomes higher than the release voltage V
DR
, elapses.
After the Release Delay Time t
DR
elapses, the output voltage V
RST
becomes equal to the input voltage V
IN
(release state). In the case of N-channel open drain architecture, the
RESET
pin goes into high impedance state,
and an output voltage V
RST
becomes equal to the pull-up voltage.
The difference between the release voltage V
DR
and the detect voltage V
DFL
is the hysteresis width V
HYS
.
The timing diagram shown below explains operation of the IXD5127xxxF - K in a typical application circuit.
At the initial state, when an input voltage V
IN
is higher than the detect voltage V
DFH
, an output voltage V
RST
is
equal to the ground voltage V
SS
.
After the elapse of the Detect Delay Time t
DF
that starts, when the input voltage V
IN
falls below the detect
voltage V
DFH
, the output voltage V
RST
is equal to the input voltage V
IN
(detection state). In the case of N-channel
© 2014 IXYS Corp.
Characteristics subject to change without notice
5
Doc. No. IXD5127_DS, Rev. N0
嵌入式系统
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