DDR SDRAM 256Mb E-die (x4, x8)
DDR SDRAM
256Mb E-die DDR SDRAM Specification
60 FBGA
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Rev. 1.3 July. 2005
DDR SDRAM 256Mb E-die (x4, x8)
Table of Contents
DDR SDRAM
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ...................................................................................................................4
3.0 Operating Frequencies................................................................................................................4
4.0 Pin Description ...........................................................................................................................5
5.0 Package Physical Dimension ....................................................................................................6
6.0 Block Diagram (16Mbit x4 / 8Mbit x8 I/O x4 Banks) .................................................................7
7.0 Input/Output Function Description ............................................................................................8
8.0 Command Truth Table.................................................................................................................9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
15.0 DDR SDRAM IDD spec table ..................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ..............................................................................17
21.0 Component Notes ....................................................................................................................18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.3 July. 2005
DDR SDRAM 256Mb E-die (x4, x8)
Revision History
Revision
1.0
1.1
1.2
1.3
Month
June
August
October
July
Year
2003
2003
2004
2005
- First version release
- Corrected typo
- Corrected typo
- Changed master format
History
DDR SDRAM
Rev. 1.3 July. 2005
DDR SDRAM 256Mb E-die (x4, x8)
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA
Leaded & Pb-Free(RoHS compliant)
package
DDR SDRAM
2.0 Ordering Information
Part No.
K4H560438E-G(Z)C/LCC
K4H560438E-G(Z)C/LB3
K4H560838E-G(Z)C/LCC
K4H560838E-G(Z)C/LB3
Org.
64M x 4
32M x 8
Max Freq.
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Interface
SSTL2
SSTL2
Package
60 FBGA
60 FBGA
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (G : 60 FBGA with Leaded, Z : 60 FBGA with Lead-free)
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
Rev. 1.3 July. 2005
DDR SDRAM 256Mb E-die (x4, x8)
4.0 Ball Description
(Bottom
View)
64M x 4
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
DDR SDRAM
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
32M x 8
1
2
3
7
8
9
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
Organization
64Mx4
32Mx8
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.3 July. 2005
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