电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

VT-704-EAE-2060-37M4642000

产品描述CMOS Output Clock Oscillator, 37.4642MHz Nom
产品类别无源元件    振荡器   
文件大小845KB,共8页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
下载文档 详细参数 全文预览

VT-704-EAE-2060-37M4642000概述

CMOS Output Clock Oscillator, 37.4642MHz Nom

VT-704-EAE-2060-37M4642000规格参数

参数名称属性值
Objectid7372250252
包装说明SMD, 4 PIN
Reach Compliance Codecompliant
Country Of OriginThailand
ECCN代码EAR99
YTEOL3
其他特性TR, 7 INCH
老化1 PPM/FIRST YEAR
最长下降时间4 ns
频率调整-机械NO
频率稳定性2%
安装特点SURFACE MOUNT
端子数量4
标称工作频率37.4642 MHz
最高工作温度85 °C
最低工作温度-40 °C
振荡器类型CMOS
输出负载15 pF
封装主体材料CERAMIC
封装等效代码DILCC4,.2,200
物理尺寸7.0mm x 5.0mm x 1.9mm
最长上升时间4 ns
最大压摆率6 mA
最大供电电压3.465 V
最小供电电压3.135 V
标称供电电压3.3 V
表面贴装YES
最大对称度55/45 %

VT-704-EAE-2060-37M4642000文档预览

VT-704
Temperature Compensated Crystal Oscillator
VT-704
Description
Vectron’s VT-704 Temperature Compensated Crystal Oscillator (TCXO) is a quartz stabilized, Clipped sine wave or CMOS output,
analog temperature compensated oscillator, operating off a 2.5V to 3.3 volt supply in a hermetically sealed 7.0 x 5.0 mm ceramic
package.
Features
Clipped Sine Wave or CMOS Output
5.000 - 52.000MHz Output Frequency
±0.5ppm Temperature Stability
Optional Frequency Tuning
Fundamental Crystal Design
Gold over nickel contact pads
Hermetically Sealed Ceramic SMD package
Applications
Femto Cells
Base Stations
IP Networking
Global Positioning Systems
Point to Point Radio
Manpack Radio
Test and Measurement
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
V
DD
Crystal
Output
Analog
Temperature
Comp.
V
CONTROL
(Optional)
Gnd
Page1
Specifications
Table 1. Electrical Performance, Clipped Sine Wave Option
Parameter
Output Frequency
1
,
Ordering Option
Supply Voltage
3
,
Ordering Option
Supply Current
Operating Temperature,
Ordering Option
Stability Over T
OP4
,
Ordering Option
Frequency Tolerance
5
Power Supply Stability, ±5%
Load Stability, ±10%
Aging / 1st year
Tuning Range
6
Tuning Slope
Control Voltage to reach Pull Range
Control Voltage Impedance
Output Level High
Output Load
Start Up Time
Phase Noise, 10.00MHz
7
10Hz
100Hz
1kHz
10kHz
100kHz
V
O
p-p
C
L
t
SU
Phase Noise
7
N
Symbol
f
O
V
DD
I
DD
T
OP
F
STAB
F
TOL
F
PWR
F
LOAD
F
AGE
Min.
5
Typ
+2.5, +2.8, +3.0, +3.3
Max
52
3.5
Units
MHz
V
mA
°C
ppm
ppm
ppm
ppm
ppm
ppm
0/55, -10/70, -20/70, -30/80, -30/85, -40/85
±0.5, ±1.0, ±1.5 , ±2.0, ±2.5, ±3.0, ±4.0, ±5.0
±2.0
±0.1
±0.2
±1.0
±5.0, ±8.0, ±10.0, ±12.0
Positive
0.5
100
1.5
2.5
Frequency Stability
Frequency Tuning (EFC),
Ordering Option
PR
V
C
V
Kohm
V
RF Output (Clipped Sine Wave),
Ordering Option
0.8
10k || 10pF
2
ms
dBc/Hz
-96
-122
-140
-148
-153
1. Refer to Table 8 for Standard Frequencies. Other Frequencies are available on request. Check with factory.
2. Output DC-cut capacitor is optional.
3. The VT-704 power supply pin (Pin4) should be filtered using a by-pass capacitor of 0.1uF for optimal performance.
4. Referenced to the midpoint between minimum and maximum frequency value over Operating Temperature Range.
5. Frequency measured at 25 °C, 1 hour after 2 IR reflows.
6. Referenced to Mid Control Voltage
7. Measured at ambient temperature using Agilent E5052B Signal Source Analyzer.
Page2
Table 2. Electrical Performance, CMOS Option
Parameter
Output Frequency
1
,
Ordering Option
Supply Voltage
3
,
Ordering Option
Supply Current
Operating Temperature,
Ordering Option
Stability Over T
OP4
,
Ordering Option
Frequency Tolerance
5
Power Supply Stability, ±5%
Load Stability, ±10%
Aging / 1st year
Tuning Range
6
Tuning Slope
Control Voltage to reach Pull Range
Control Voltage Impedance
Output Level High
Output Level Low
Output Load
Duty Cycle
Start Up Time
Rise & Fall Times
Phase Noise
7
Phase Noise, 10.00MHz
7
10Hz
100Hz
1kHz
10kHz
100kHz
N
Symbol
f
O
V
DD
I
DD
T
OP
F
STAB
F
TOL
F
PWR
F
LOAD
F
AGE
Min.
5
Typ
+2.5, +2.8, +3.0, +3.3
Max
52
6.0
Units
MHz
V
mA
°C
ppm
ppm
ppm
ppm
ppm
ppm
0/55, -10/70, -20/70, -30/80, -30/85, -40/85
±0.5, ±1.0, ±1.5 , ±2.0, ±2.5, ±3.0, ±4.0, ±5.0
±2.0
±0.1
±0.2
±1.0
±5.0, ±8.0, ±10.0, ±12.0
Positive
0.5
100
1.5
2.5
Frequency Stability
Frequency Tuning (EFC),
Ordering Option
PR
V
C
V
Kohm
V
RF Output (CMOS),
Ordering Option
V
OH
V
OL
C
L
45
t
SU
0.9*V
DD
0.1*V
DD
15
55
2
4
pF
%
ms
ns
dBc/Hz
-98
-129
-145
-153
-156
1. Refer to Table 8 for Standard Frequencies. Other Frequencies are available on request. Check with factory.
2. Output DC-cut capacitor is optional.
3. The VT-704 power supply pin (Pin4) should be filtered using a by-pass capacitor of 0.1uF for optimal performance.
4. Referenced to the midpoint between minimum and maximum frequency value over Operating Temperature Range.
5. Frequency measured at 25 °C, 1 hour after 2 IR reflows.
6. Referenced to Mid Control Voltage.
7. Measured at ambient temperature using Agilent E5052B Signal Source Analyzer
Page3
Phase Noise Performance for 10MHz Clipped Sine Wave
Phase Noise Performance for 10MHz CMOS
Page4
Package Outline Drawing & Pad Layout
XXMXXX
YYWW T
Dimensions in mm
Table 3. Pinout
Pin #
1
Marking Information
XXMXX - Frequency (Example: 10M000)
YY - Year of Manufacture
WW - Week of the Year
T - Manufacturing Location
- Pin 1 Indicator
2
3
4
Symbol
Vc or NC
GND
OUT
V
DD
Function
TCXO Control Voltage or No Connect
Ground
RF Output
Supply Voltage
Note:
0.1uF capacitor is a by-pass power supply filter capacitor
placed between Pin4 (Vdd) and Ground for optimal
performance.
VCXO Function
S
VCXO Feature:
The VT-704 is supplied with a VCXO function for applications were it will be used in a PLL, or the output frequency needs
fine tune or calibration adjustments. This is a high impedance input, 100kOhm, and can be driven with an op-amp or terminated with
adjustable resistors etc.
Pin1 should not be left floating on the VCXO optional device.
Maximum Ratings
S
Absolute Maximum Ratings and Handling Precautions
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other
excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended
periods may adversely affect device reliability.
Although ESD protection circuitry has been designed into the VT-704, proper precautions should be taken when handling and mounting,
VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation.
ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for
the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes.
Table 4. Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Control Voltage
Enable/Disable Voltage
ESD, Human Body Model
ESD, Charged Device Model
Symbol
T
STORE
V
DD
V
C
E/D
Rating
-55/125
-0.6/6
-0.6/V
DD
+0.6
-0.6/V
DD
+0.6
1500
1000
Unit
ºC
V
V
V
V
V
Page5
看各大厂商ssd生产过程
首先是OCZ 原文地址 OCZ在固态硬盘市场的经历大体可以分为两个阶段——在没被东芝收购之前,他们在SSD市场闯出了一片天地,还坚持自主研发主控,但作为一家小公司,OCZ在NAND闪存货源上得 ......
白丁 FPGA/CPLD
非法集资21.19亿,中兴前工会主席被判二十年
来源 钛媒体   近日,裁判文书网披露的一份判决书显示,中兴通讯原工会主席何某梅犯集资诈骗罪、职务侵占罪等,非法募集资金21.19亿,未退还资金8.99亿元,被决定执行有期徒刑二十年,并处 ......
eric_wang 聊聊、笑笑、闹闹
喜欢做技术的人不喜欢写帖子
以前我就是这样,在弄51时,我会沉浸在代码的欢乐中. 早段时间算学ARM,最近又参加众多的面试.慢慢地我喜欢看帖回帖,更喜欢写帖子... 当看到某些人能写出一篇耐人寻味的文章时 ......
呱呱 单片机
如何定位子程序位置
就是定位变量和程序的位置...
aeiou stm32/stm8
SJF2440不能烧写Nor Flash.
我的SJF2440不能烧写MX 29LV160这个NOR Flash,读不到ID,我检察了发送命令的顺序没有错误.请大家指教....
Dani 嵌入式系统
DSP硬件实现的优化(二)—复数乘法中出现共轭时的资源优化
在数字信号处理中,有时候会出现两个复数相乘,而其中一个被乘数为原始输入数的共轭的情况。举个例子:有两个输入信号: x1 = a+b*i, x2 = c+d*i; y = x1*conj(x2) = (a+b*i)*(c-d*i) = (a* ......
fish001 DSP 与 ARM 处理器

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2436  2184  1258  512  484  50  44  26  11  10 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved