dsPIC33CK256MP508 FAMILY
28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers
with High-Resolution PWM and CAN Flexible Data (CAN FD)
Operating Conditions
• 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS
• 3.0V to 3.6V, -40°C to +150°C, DC to 70 MIPS
Power Management
• Low-Power Management Modes (Sleep,
Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
Core: 16-Bit dsPIC33CK CPU
• 32-256 Kbytes of Program Flash with ECC and
8-24K RAM
• Fast 6-Cycle Divide
• LiveUpdate
• Code Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL Plus
Hardware Divide
• 32-Bit Multiply Support
• Four Sets of Interrupt Context Saving Registers
which Include Accumulator and STATUS for Fast
Interrupt Handling
• Zero Overhead Looping
• RAM Memory Built-In Self-Test (MBIST)
High-Speed PWM
•
•
•
•
•
•
8 PWM Pairs
Up to 250 ps PWM Resolution
Dead Time for Rising and Falling Edges
Dead-Time Compensation
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Fault and Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
Timers/Output Compare/Input Capture
• One General Purpose Timer
• Peripheral Trigger Generator (PTG):
- Up to 15 trigger sources to other
peripheral modules
- CPU independent state machine-based
instruction sequencer
• Nine MCCP/SCCP modules which Include Timer,
Capture/Compare and PWM:
- 1 MCCP
- 8 SCCPs
- 16 or 32-bit time base
- 16 or 32-bit capture
- 4-deep capture buffer
• Fully Asynchronous Operation, Available in
Sleep Modes
Clock Management
•
•
•
•
•
•
Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Reference Clock Output
Fail-Safe Clock Monitor (FSCM)
Fast Wake-up and Start-up
Backup Internal Oscillator
2017-2020 Microchip Technology Inc.
DS70005349H-page 1
dsPIC33CK256MP508 FAMILY
Advanced Analog Features
• High-Speed ADC module:
- 12-bit with two dedicated SAR ADC cores
and one shared SAR ADC core
- Configurable resolution (up to 12-bit) for each
ADC core
- Up to 3.5 Msps conversion rate per channel
at 12-bit resolution
- Up to 24 input channels
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Four digital comparators
- Four oversampling filters for increased resolution
• Up to Three Analog Comparators:
- 15 ns analog comparator
• Up to Three Op Amps
• Three 12-Bit DACs:
- Hardware slope compensation
Direct Memory Access (DMA)
• Four DMA Channels
Debugger Development Support
• In-Circuit and In-Application Programming and
Debugging
• Three Complex, Five Simple Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace Buffer and Run-Time Watch
Safety Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock Monitor System with Backup Oscillator
DMT (Deadman Timer)
ECC (Error Correcting Code)
WDT (Watchdog Timer)
CodeGuard™ Security
CRC (Cyclic Redundancy Check)
Flash OTP by ICSP™ Write Inhibit
RAM Memory Built-In Self-Test (MBIST)
Two-Speed Start-up
Fail-Safe Clock Monitoring (FSCM)
Backup FRC (BFRC)
Capless Internal Voltage Regulator
Virtual Pins for Redundancy and Monitoring
Communication Interfaces
• Three Protocol UARTs with Automated Protocol
Handling Support for:
- LIN 2.2
- DMX
- IrDA
®
• Three 4-Wire SPI/I
2
S modules
• CAN Flexible Data (FD) module
• Three I
2
C modules with SMBus Support
• PPS to Allow Function Remap
• Programmable Cyclic Redundancy Check (CRC)
• Two SENT modules
• Parallel Master Port (PMP)
Functional Safety
• Class B Safety Library – IEC 60730
• For ASIL B and Beyond Applications – ISO 26262
• FMEDA Computation Spreadsheet (Evaluation of
Random Hardware Failures Metric)
• Functional Safety Manual
• Functional Safety Diagnostics Suite
Qualification Support
• AEC-Q100 REV-H (Grade 1: -40°C to +125°C)
Compliant
• AEC-Q100 REV-H (Grade 0: -40°C to +150°C)
Compliant
DS70005349H-page 2
2017-2020 Microchip Technology Inc.
dsPIC33CK256MP508 PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in
Table 1
and
Table 2.
The following pages show their pinout diagrams.
Analog Comparators
2017-2020 Microchip Technology Inc.
DS70005349H-page 3
TABLE 1:
dsPIC33CK256MP508 FAMILY WITH CAN FD
DMA Channels
ADC Channels
PWM Outputs
MCCP/SCCP
ADC Module
Product
dsPIC33CK256MP508
dsPIC33CK256MP506
dsPIC33CK256MP505
dsPIC33CK256MP503
dsPIC33CK256MP502
dsPIC33CK128MP508
dsPIC33CK128MP506
dsPIC33CK128MP505
dsPIC33CK128MP503
dsPIC33CK128MP502
dsPIC33CK64MP508
dsPIC33CK64MP506
dsPIC33CK64MP505
dsPIC33CK64MP503
dsPIC33CK64MP502
dsPIC33CK32MP506
dsPIC33CK32MP505
dsPIC33CK32MP503
dsPIC33CK32MP502
80
64
48
36
28
80
64
48
36
28
80
64
48
36
28
64
48
36
28
256K
256K
256K
256K
256K
128K
128K
128K
128K
128K
64K
64K
64K
64K
64K
32K
32K
32K
32K
24K
24K
24K
24K
24K
16K
16K
16K
16K
16K
8K
8K
8K
8K
8K
8K
8K
8K
8K
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
24
20
19
16
12
24
20
19
16
12
24
20
19
16
12
20
19
16
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
8
8
6
4
8
8
8
6
4
8
8
8
6
4
8
8
6
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
3
3
3
2
3
3
3
3
2
3
3
3
2
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
0
REFO Clock
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
12-Bit DAC
Data RAM
Op Amp
CAN FD
Timers
UART
SENT
Flash
CRC
PMP
Pins
PTG
CLC
QEI
SPI
I
2
C
dsPIC33CK256MP508 FAMILY
Analog Comparators
DMA Channels
ADC Channels
PWM Outputs
MCCP/SCCP
ADC Module
Product
dsPIC33CK256MP208
dsPIC33CK256MP206
dsPIC33CK256MP205
dsPIC33CK256MP203
dsPIC33CK256MP202
dsPIC33CK128MP208
dsPIC33CK128MP206
dsPIC33CK128MP205
dsPIC33CK128MP203
dsPIC33CK128MP202
dsPIC33CK64MP208
dsPIC33CK64MP206
dsPIC33CK64MP205
dsPIC33CK64MP203
dsPIC33CK64MP202
dsPIC33CK32MP206
dsPIC33CK32MP205
dsPIC33CK32MP203
dsPIC33CK32MP202
2017-2020 Microchip Technology Inc.
80
64
48
36
28
80
64
48
36
28
80
64
48
36
28
64
48
36
28
256K 24K
256K 24K
256K 24K
256K 24K
256K 24K
128K 16K
128K 16K
128K 16K
128K 16K
128K 16K
64K
64K
64K
64K
64K
32K
32K
32K
32K
8K
8K
8K
8K
8K
8K
8K
8K
8K
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
24
20
19
16
12
24
20
19
16
12
24
20
19
16
12
20
19
16
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
1/8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
8
8
6
4
8
8
8
6
4
8
8
8
6
4
8
8
6
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
3
3
3
2
3
3
3
3
2
3
3
3
2
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
0
REFO Clock
12-Bit DAC
Data RAM
Op Amp
CAN FD
Timers
DS70005349H-page 4
dsPIC33CK256MP508 FAMILY
TABLE 2:
dsPIC33CK256MP508 FAMILY WITHOUT CAN FD
UART
SENT
Flash
CRC
PMP
Pins
CLC
PTG
QEI
SPI
I
2
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
dsPIC33CK256MP508 FAMILY
Pin Diagrams
28-Pin SSOP
RA1
RA2
RA3
RA4
AV
DD
AV
SS
V
DD
V
SS
RB0
RB1
RB2
RB3
RB4
RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RA0
MCLR
RB15
RB14
RB13
RB12
RB11
RB10
V
DD
V
SS
RB9
RB8
RB7
RB6
Note:
Shaded pins are up to 5 VDC tolerant.
TABLE 3:
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note 1:
2:
3:
28-PIN SSOP
(1)
Function
Pin #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PGC3/RP38/SCL2/RB6
TDO/AN2/CMP3A/RP39/SDA3/RB7
PGD1/AN10/RP40/SCL1/RB8
PGC1/AN11/RP41/SDA1/RB9
V
SS
V
DD
TMS/RP42/PWM3H/RB10
(2)
TCK/RP43/PWM3L/RB11
TDI/RP44/PWM2H/RB12
RP45/PWM2L/RB13
RP46/PWM1H/RB14
RP47/PWM1L/RB15
MCLR
OA1OUT/AN0/CMP1A/IBIAS0/RA0
Function
OA1IN-/ANA1/RA1
OA1IN+/AN9/RA2
DACOUT1/AN3/CMP1C/RA3
AN4/CMP3B/IBIAS3/RA4
AV
DD
AV
SS
V
DD
V
SS
OSCI/CLKI/AN5/RP32/RB0
OSCO/CLKO/AN6/RP33/RB1
(3)
OA2OUT/AN1/AN7/ANA0/CMP1D/CMP2D/CMP3D/RP34/
SCL3/INT0/RB2
PGD2/OA2IN-/AN8/RP35/RB3
PGC2/OA2IN+/RP36/RB4
PGD3/RP37/SDA2/RB5
RPn
represents remappable peripheral functions.
A pull-up resistor is connected to this pin when device is erased (JTAG enabled) and during programming.
This pin is toggled during programming.
2017-2020 Microchip Technology Inc.
dsPIC33CKXXXMP202
dsPIC33CKXXXMP502
DS70005349H-page 5
FPGA/CPLD
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