FLAT PACK
Q-TECH
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
Description
Q-Tech’s flat pack crystal oscillators consist of a source
clock square wave generator, logic output buffers
and/or logic divider stages, and a round A high-
T
precision quartz crystal built in an all metal flat
package.
Features
• Made in the USA
• ECCN: 3A001.b.10
• DFARS 252-225-7014 Compliant:
Electronic Component Exemption
• USML Registration # M17677
• Wide frequency range from 0.12Hz to 200MHz
• Available as QPL MIL-PRF-55310/21 (TTL)
QT24 only
• Choice of flat packs and pin outs
• Choice of supply voltages
• Choice of output logic options
• A
T-Cut crystal
• All metal hermetically sealed package
• Tight or custom symmetry available
• Capacitive load drive capability (Z output)
• Low height
• External tuning capacitor option
• Fundamental and third overtone designs
• Tristate function option D
• Three-point crystal mounts
• Custom design available tailors to meet
customer’s needs
• Q-Tech does not use pure lead or pure tin in its
products
• RoHS compliant
Ordering Information
Sample part number
QT 24 A CD 1 0M - 2 0. 00 0 M Hz
QT 24 AC D 10 M - 20.000MHz
T = Standard
S = Solder Dip (*)
Model #
(See page 3)
C
AC
HC
T
L
N
R
E
EH
EF
PE
LP
Z
=
=
=
=
=
=
=
=
=
=
=
=
=
CMOS +5V to +15V (**)
ACMOS +5V
HCMOS +5V
TTL +5V
LVHCMOS +3.3V
LVHCMOS +2.5V
LVHCMOS +1.8V
10K ECL -5.2V
10KH ECL -5.2V
100K/300K ECL -4.5V
PECL +5V
PECL +3.3V
Z output
Screened to
MIL-PRF-55310,level B
(Left blank if no screening)
Output frequency
Tristate Option D
(Left blank if no Tristate)
1=
4=
5=
6=
9=
10 =
11 =
12 =
± 100ppm at
0ºC to +70ºC
± 50ppm at
0ºC to +70ºC
± 25ppm at -20ºC to +70ºC
± 50ppm at -55ºC to +105ºC
± 50ppm at -55ºC to +125ºC
± 100ppm at -55ºC to +125ºC
± 50ppm at -40ºC to +85ºC
± 100ppm at -40ºC to +85ºC
(*) Hot Solder Dip Sn60 per MIL-PRF 55310 is optional for an additional cost
(**) Please specify supply voltage when ordering CMOS
For frequency stability vs. temperature options not listed herein, request a custom
part number.
For Non-Standard requirements, contact Q-Tech Corporation at
Sales@Q-Tech.com
Applications
• Designed to meet today’s requirements for all
voltage applications
• Wide military clock applications
• Industrial controls
• Microcontroller driver
Packaging Options
• Standard packaging in a locked anti-static cardboard
Other Options Available For An Additional Charge
• Lead forming available on all packages. Please contact for details.
• P. I. N. D. test (MIL-STD 883, Method 2020)
• Lead trimming
All Flat Pack packages are available in surface mount form.
Specifications subject to change without prior notice.
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Flat Pack (Revision E, June 2010) (ECO# 9856)
1
FLAT PACK
Q-TECH
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
Electrical Characteristics
Parameters
Output freq. range QT21, 24, 25
(Fo)
QT22, 26, 28
Supply voltage (Vdd)
C
500Hz — 15MHz
500Hz — 15MHz
5V ~ 15Vdc ± 10%
AC
500Hz — 125MHz
500Hz — 85MHz
HC
0.12Hz — 125MHz
500Hz — 85MHz
5.0Vdc ± 10%
T
0.12Hz — 125MHz
500Hz — 85MHz
L (*)
0.12Hz — 160MHz
500Hz — 85MHz
3.3Vdc ± 10%
ECL / PECL (**)
1MHz — 200MHz
8MHz — 85MHz
-5.2Vdc ± 5% (10K / 10KHECL)
5Vdc ± 5% (PECL)
3.3Vdc ± 5% (LVPECL)
0 to -8.0Vdc (10K / 10KHECL)
0 to +8.0Vdc (PECL)
0 to +5.0Vdc (LVPECL)
Maximum Applied Voltage (Vdd max.)
Freq. stability (∆F/∆T)
Operating temp. (Topr)
Storage temp. (Tsto)
-0.5 to +18Vdc
-0.5 to +7.0Vdc
See Option codes
See Option codes
-62ºC to + 125ºC
-0.5 to +5.0Vdc
Operating supply current
(Idd) (No Load)
F and Vdd dependent
3 mA max. at 5V up to 5MHz
25 mA max. at 15V up to 15MHz
20 mA max. -
25 mA max. -
35 mA max. -
45 mA max. -
60 mA max. -
0.12Hz ~
16MHz ~
40MHz ~
60MHz ~
85MHz ~
<
<
<
<
16MHz
40MHz
60MHz
85MHz
125MHz
3 mA max. - 0.12Hz ~ < 500kHz
6 mA max. - 500kHz ~ < 16MHz
10 mA max. - 16MHz ~ < 32MHz
20 mA max. - 32MHz ~ < 60MHz
30 mA max. - 60MHz ~ < 100MHz
40 mA max. - 100MHz ~ < 130MHz
50 mA max. - 130MHz ~ 160MHz
45 mA max. - 8MHz ~ < 125MHz
75 mA max. - 125MHz ~ 200MHz
Symmetry
(50% of ouput waveform or 1.4Vdc for
TTL)
Rise and Fall times
(with typical load)
45/55% max. Fo < 4MHz
40/60% max. Fo ≥ 4MHz
30ns max.
(Measured from 10% to 90%)
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
15ns max. Fo < 15kHz
6ns max. Fo 15kHz ~ 39.999MHz
3ns max. Fo 40MHz ~ 160 MHz
(Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL)
15pF // 10kΩ
10TTL Fo < 20MHz
6TTL Fo ≥ 20MHz
10ms max.
15pF // 10kΩ
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
3.5ns max. Fo < 125MHz
3ns max. Fo 125MHz ~ 200MHz
(Measured from 20% to 80%)
50Ω to -2V (10K / 10KH)
50Ω to Vcc -2V (P & LP)
Output Load
Start-up time (Tstup)
0.9 x Vdd min.; 0.1 x Vdd max.
Output voltage (Voh/Vol)
Output Current (Ioh/Iol)
Enable/Disable
Tristate function
Jitter RMS 1σ (at 25ºC)
Aging (at 70ºC)
± 1mA typ. at 5V
± 6.8mA typ. at 15V
Call for details
± 24mA
±8 mA
VIH ≥ 2.2V Oscillation;
VIL ≤ 0.8V High Impedance
8ps typ. - < 40MHz
5ps typ. - ≥ 40MHz
2.4V min.; 0.4V max.
0.9 x Vdd min.; 0.1 x Vdd max.
-1.15V min; -1.54V max. (E)
4V min.; 3.37V max. (PE)
2.27V min.; 1.68V max. (LP)
-50mA
Call for details
Integrated phase jitter
12kHz - 20MHz 1ps typ.
-1.6mA / TTL
+40μA / TTL
± 4mA .
VIH ≥ 0.7 x Vdd Oscillation;
VIL ≤ 0.3 x Vdd High Impedance
15ps typ. - < 40MHz
8ps typ. - ≥ 40MHz
± 5ppm max. first year / ± 2ppm typ. per year thereafter
(*) Available in 2.5Vdc (N) or 1.8Vdc (R)
(**) Please contact Q-Tech for details on 100KECL logic (EF)
Z Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf)
Q-TECH Corporation
-
10150 W. Jefferson Boulevard, Culver City 90232
-
Tel: 310-836-7900 - Fax: 310-836-2157
-
www.q-t e ch .co m
Flat Pack (Revision E, June 2010) (ECO# 9856)
2
FLAT PACK
Q-TECH
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
Package Configuration Versus Pin Connections
A
QT21
Q-TECH
P/N
FREQ.
D/C S/N
B
QT22
C
QT24
Q-TECH
P/N
FREQ.
D/C S/N
D
QT25
Q-TECH
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
D/C S/N
.140
(3.56)
.120
(3.05)
MAX.
.120
(3.05)
.150
MAX.
(3.81)
MAX.
.060/.035
.085/.070
(2.16/1.78)
.010
(.254)
.010
(.254)
.060/.045
(1.52/1.14)
.010
(.254)
.060/.045
(1.52/1.14)
.010
(.254)
(1.52/.889)
.625
.050
(1.27)
10
(15.88)
SQ.
.375
.050
(1.27)
11
.625
.050
(1.27)
(15.88)
SQ.
.050
(1.27)
11
.625
(15.88)
SQ.
(9.53)
8
9
.500
(12.70)
10
10
11
.450
(11.43)
.350
(8.89)
1
.015
(.381)
.500
MIN.
.450
(11.43)
.450
(11.43)
16
1
20
1
.015
(.381)
20
.500
1
.015
.500
MIN.
20
.500
.015
(.381)
(12.70)
(12.70)
(.381)
MIN.
MIN.
(12.70)
(12.70)
E
QT26
Q-TECH
F
QT28
QT # Conf Vcc
GND Case
10
9
10
10
7
9
10
9
10
10
7
9
Output
(*)
11
10
11
11
8
10
E/D
or
N/C
12
11
12
12
6
11
Equivalent
MIL-PRF-55310
Configuration
N/A
N/A
/21 = QT24T
N/A
N/A
N/A
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
D/C S/N
QT21
QT22
QT24
MAX.
A
B
C
D
E
F
13
8
13
13
14
8
.160
(4.06)
MAX.
.120
(3.05)
QT25
.070
(1.78)
.590
.010
(.254)
.05
MIN.
(1.27)
.05
MIN.
(1.27)
.010
(.254)
QT26
QT28
.375
.100
(2.54)
(14.99)
.050
(1.27)
8
(9.53)
9
(*) ECL / PECL complimentary output available on pin 12
.500
(12.70)
7
8
.790
.600
(15.24)
(20.07)
(except QT22, 26, & 28) with a Q-Tech custom part number
.350
(8.89)
1
16
.15
(3.81)
Package Information
• Package material (Header and Leads): Kovar
• Lead finish: Gold Plated – 50µ ~ 80µ inches
Nickel Underplate – 100µ ~ 250µ inches
• Cover: Kovar, Gold Plated – 50µ ~ 100µ inches
Nickel Underplate – 70µ ~ 90µ inches
• Package to lid attachment: Seam weld
• Weight: 2.0g typ., 4.0g max.
.015
(.381)
1
.015
(.381)
14
.500
(12.70)
MIN.
Dimensions are in inches (mm)
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Flat Pack (Revision E, June 2010) (ECO# 9856)
3
FLAT PACK
Q-TECH
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
Test Circuit
Output Waveform (Typical)
SYMMETRY =
TH
T
Typical test circuit for ECL logic.
x 100%
Tr
mA
+
POWER
SUPPLY
-
+
Vdc
-
0.1µF
or
0.01µF
-2Vdc
-4.5V
or
-5.2V
GND
OUT
Vee
50Ω
OUT
Tf
Vdd
0.9xVdd
VOH
0.5xVdd
0.1xVdd
VOL
TH
T
GND
Startup Time
Typical test circuit for TTL logic.
Vdd
TYPICAL SET-UP FOR START-UP TIME
RL
+
mA
-
+
Vdc
-
0.1µF
or
0.01µF
Vdd OUT
OUT
E/D GND
CL
Rs
Oscilloscope
54616B Agilent
Variable Ramp
+
POWER
SUPPLY
-
DUT
LOAD
6 TTL
10 TTL
CL(*)
12pF
20pF
RL
430Ω
270Ω
RS
10kΩ
6kΩ
Ts
Start-up box
(*) CL inclides the loading effect of the oscilloscope probe.
Supply Current
Typical test circuit for CMOS logic
TYPICAL SUPPLY CURRENT ICC (mA) AT 3.3Vdc & 5.0Vdc CMOS Logic NO LOAD
+ mA
+
Power
supply
-
+
Vdc
Vdd Out
0.1µF
or
E/D GND
0.01µF
Output
45
40
35
30
Icc (mA)
-
15pF
(*)
10k
Ground
25
20
15
10
Tristate Function
(*) CL includes probe and jig capacitance
5
0
0.5 2
8
16 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160
Freq(MHz)
Icc 3.3V
Icc 5V
The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it
can be left floating or tied to Vdd without deteriorating the electrical performance.
Frequency vs. Temperature Curve
50
40
30
Frequency Stability (PPM)
20
10
0
-10
-20
-30
-40
-50
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
2_5
35
3_5
40
4_5
45
5_5
50
55
60
65
70
75
80
85
90
95
100 105 110 115 120 125
Temperature (°C)
FREQUENCY STABILITY VERSUS TEMPERATURE QT24T- 48.000MHz
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Flat Pack (Revision E, June 2010) (ECO# 9856)
4
FLAT PACK
Q-TECH
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
Thermal Characteristics
The heat transfer model in a hybrid package is described in
figure 1.
D/A epoxy
D/A epoxy
Die
45º
Heat
Hybrid Case
45º
Substrate
Heat spreading occurs when heat flows into a material layer of
increased cross-sectional area. It is adequate to assume that
spreading occurs at a 45° angle.
The total thermal resistance is calculated by summing the
thermal resistances of each material in the thermal path
between the device and hybrid case.
RT = R1 + R2 + R3 + R4 + R5
The total thermal resistance RT (see figure 2) between the heat
source (die) to the hybrid case is the Theta Junction to Case
(Theta JC) in°C/W.
• Theta junction to case (Theta JC) for this product is 30°C/W.
• Theta case to ambient (Theta CA) for this part is 100°C/W.
• Theta Junction to ambient (Theta JA) is 130°C/W.
Maximum power dissipation PD for this package at 25°C is:
• PD(max) = (TJ (max) – TA)/Theta JA
• With TJ = 175°C (Maximum junction temperature of die)
• PD(max) = (175 – 25)/130 = 1.15W
JA
R1
R2
R3
R4
R5
Die
D/A epoxy
Substrate
D/A epoxy
Hybrid Case
(Figure 1)
T
CA
A
T
C
JC
T
J
Die
JC
CA
(Figure 2)
Environmental Specifications
Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Flat Packs. Q-Tech can also customize screening and test
procedures to meet your specific requirements. The Flat Packs are designed and processed to exceed the following test conditions:
Environmental Test
Temperature cycling
Constant acceleration
Seal: Fine and Gross Leak
Burn-in
Aging
Vibration sinusoidal
Shock, non operating
Thermal shock, non operating
Ambient pressure, non operating
Resistance to solder heat
Moisture resistance
Terminal strength
Resistance to solvents
Solderability
ESD Classification
Moisture Sensitivity Level
Test Conditions
MIL-STD-883, Method 1010, Cond. B
MIL-STD-883, Method 2001, Cond. A, Y1
MIL-STD-883, Method 1014, Cond. A and C
160 hours, 125°C with load
30 days, 70°C, ± 1.5ppm max
MIL-STD-202, Method 204, Cond. D
MIL-STD-202, Method 213, Cond. I
MIL-STD-202, Method 107, Cond. B
MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum
MIL-STD-202, Method 210, Cond. C
MIL-STD-202, Method 106
MIL-STD-202, Method 211, Cond. C
MIL-STD-202, Method 215
MIL-STD-202, Method 208
MIL-STD-883, Method 3015, Class 1HBM 0 to 1,999V
J-STD-020, MSL=1
Please contact Q-Tech for higher shock requirements
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Flat Pack (Revision E, June 2010) (ECO# 9856)
5
求职招聘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
