BU-62743/62843/62864
PCI ENHANCED MINIATURE ADVANCED
COMMUNICATION ENGINE
(PCI ENHANCED MINI-ACE ™)
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has...
®
FEATURES
•
32-Bit/33MHz, 3.3Volt, PCI Target
Interface
•
Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
•
Compatible with Enhanced Mini-ACE,
Mini-ACE (Plus) and ACE Generations
•
Choice of:
•
RT only with 4K RAM (BU-62743)
•
BC/RT/MT with 4K RAM (BU-62843)
•
BC/RT/MT with 64K RAM, with RAM
Parity (BU-62864)
Actual Size:
1.0” Square Package
•
3.3V Logic
•
5V Transceiver. Available with 1760 or
McAir Compatible Options
•
1.0-inch square, 72-Pin Flatpack /
Formed Gull Lead Ceramic Package
•
Choice of 10, 12, 16, or 20MHz 1553
Clock
•
Highly Autonomous BC with Built-in
Message Sequence Control:
•
Frame Scheduling
•
Branching
•
Asynchronous Message Insertion
•
General Purpose Queue
•
User-defined Interrupts
•
Advanced RT Functions:
•
Global Circular Buffering
•
Interrupt Status Queue
•
50% Circular Buffer Rollover
Interrupts
•
Selective Message Monitor or
RT/Monitor
DESCRIPTION
The PCI Enhanced Mini-ACE family of MIL-STD-1553 terminals pro-
vides a complete interface between a 32-Bit / 33MHz PCI Bus and a
MIL-STD-1553 bus. These terminals integrate dual transceiver, proto-
col logic, and 4K words or 64K words of RAM.
With a 1.0-inch square package, the PCI Enhanced Mini-ACE is near-
ly 100% footprint and software compatible with the Enhanced Mini-
ACE, previous generation Mini-ACE (Plus) terminals, and is software
compatible with the older ACE series.
The PCI portion of the PCI Enhanced Mini-ACE is powered by 3.3V.
The PCI interface is NOT 5V tolerant.
Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, includ-
ing versions incorporating McAir compatible transmitters, is provided.
There is a choice of 10, 12, 16, or 20 MHz 1553 clocks. The BC/RT/MT
versions with 64K words of RAM include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with
a set of 20 instructions. This provides an autonomous means of
implementing multi-frame message scheduling, message retry
schemes, data double buffering, asynchronous message insertion,
and reporting to the host CPU.
The PCI Enhanced Mini-ACE RT offers the choices of single and cir-
cular buffering, along with a global circular buffering option, 50%
rollover interrupt for circular buffers, and an interrupt status queue.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2002 Data Device Corporation
Data Device Corporation
www.ddc-web.com
4K X 16
OR
64K X 17
SHARED
RAM
TRANSCEIVER
A
PAR
DATA BUS
32 X 32
WRITE
FIFO
AD31 - AD0
TX/RX_A
CH. A
PCI Address/Data, Parity,
and Bus Command/Byte Enable
TX/RX_A
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
TX_INH_A/B
C/BE3# - C/BE#0
TX/RX_B
FRAME#, IRDY#, IDSEL
CH. B
TRANSCEIVER
B
33 MHZ,
32-BIT
PCI SLAVE
INTERFACE
PCI Control
TRDY#, STOP#, DEVSEL#,
PERR#, SERR#
2
RTAD4-RTAD0, RTADP
RT-AD-LAT
TX/RX_B
(PCI) CLK
PCI CLK
RT ADDRESS AND
ADDRESS LATCH
INT A#
PCI Interrupt
INCMD/MCRST
MISCELLANEOUS
CLK_IN, MSTCLR, SSFLAG/EXT_TRG
BU-62743/62843/62864
F-11/06-0
FIGURE 1. PCI ENHANCED MINI-ACE BLOCK DIAGRAM
TABLE 1. PCI ENHANCED MINI-ACE SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
•
Logic +3.3V
•
RAM +5V
•
Transceiver +5V (Note 13)
Logic
•
Voltage Input Range
•
Voltage Input Range, 5v
Tolerant pins (Note 16)
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
•
Direct Coupled Across 35 ohms
Measured on Bus
•
Transformer Coupled Across
70 ohms
(BU-62XXXXX-XX0,
BU-62XXXXX-XX2) (Note 14)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
(BU-62XXXX3,
BU-62XXXX4)
LOGIC
V
IH
All signals except PCI
V
IL
All signals except PCI
Schmidt Hysteresis
All signals except PCI
I
IH
, I
IL
All signals except PCI
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IN
=2.7V)
I
IL
(Vcc=3.6V, V
IN
=0.4V)
V
OH
(Vcc=3.0V, I
OH
=max)
V
OL
(Vcc=3.0V, I
OL
=max)
I
OL
I
OH
C
I
(Input Capacitance)
PCI LOGIC (see PCI spec 3.3V
signaling environment)
C
I
(Input Capacitance) all PCI
except PCI_CLK&IDSEL
C
I
(Input Capacitance)PCI_CLK
C
I
(Input Capacitance) IDSEL
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
+5V (RAM for 62864),
+3.3V (Logic) Vcc
+5V (Ch. A, Ch. B)
MIN
TYP
MAX
UNITS
TABLE 1. PCI ENHANCED MINI-ACE SPECIFICATIONS
(CONT.)
PARAMETER
Current Drain (Total Hybrid)
•
BU-62864XX-XX0
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V (Logic)
•
BU-62864XX-XX2
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V (Logic)
•
BU-62743XX-XX0, BU-62843XX-XX0
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
•
BU-62743XX-XX0, BU-62843XX-XX2
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
POWER DISSIPATION
(NOTE 15)
Total Hybrid
•
BU-62864XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-62864XX-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-62743XX-XX0, BU-62843XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-62743XX-XX2, BU-62843XX-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
•
BU-62XXXXX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-62XXXXX-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
2.5
4.0
6.0
7.0
Vdd+0.3
6.0
V
V
V
V
V
kΩ
66
163
260
454
25
120
225
330
540
40
mA
mA
mA
mA
mA
5
0.200
0.860
10
pF
Vp-p
Vpeak
66
174
282
498
25
120
236
352
585
40
mA
mA
mA
mA
mA
6
7
9
Vp-p
65
169
273
481
25
100
205
310
520
40
mA
mA
mA
mA
mA
18
20
20
22
27
27
10
250
Vp-p
Vp-p
mVp-p
mVp-p
-250
150
65
180
295
525
25
100
216
332
565
40
mA
mA
mA
mA
mA
100
200
150
250
300
300
nsec
nsec
2.1
0.7
0.4
V
V
V
μA
μA
μA
V
V
mA
mA
pF
0.44
0.75
1.05
1.66
0.44
0.80
1.17
1.89
0.41
0.70
0.94
1.40
0.41
0.72
0.97
1.45
0.80
1.03
1.26
1.71
0.80
1.09
1.39
1.97
0.63
0.85
1.07
1.51
0.63
0.86
1.09
1.56
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-10
-100
-100
2.4
3.4
10
-33
-33
0.4
-3.4
50
16
11
13
pF
pF
pF
0.18
0.42
0.66
1.14
0.18
0.48
0.78
1.39
0.28
0.51
0.75
1.22
0.28
0.58
0.88
1.48
W
W
W
W
W
W
W
W
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.5
V
V
V
Data Device Corporation
www.ddc-web.com
3
BU-62743/62843/62864
F-11/06-0
TABLE 1. PCI ENHANCED MINI-ACE SPECIFICATIONS
(CONT.)
PARAMETER
CLOCK INPUTS
PCI Clock Input Frequency
•
1553 Clock Frequency
• Default Mode
• Option
• Option
• Option
•
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
•
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next Message
(for Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
MIN
TYP
MAX UNITS
33.3
16.0
12.0
10.0
20.0
-0.01
-0.10
-0.001
-0.01
2.5
0.01
0.10
0.001
0.01
MHz
MHz
MHz
MHz
MHz
%
%
%
%
µs
TABLE 1 NOTES: (Cont’d)
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub side
(either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8)
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses dur-
ing BC Start-of-Message (SOM) and End-of-Message (EOM) trans-
fer sequences could have the effect of lengthening the intermessage
gap time. For each host access during an SOM or EOM sequence,
the intermessage gap time will be lengthened by 6 clock cycles.
Since there are 7 internal transfers during SOM and 5 during EOM,
this could theoretically lengthen the intermessage gap by up to 72
clock cycles; i.e., up to 7.2 µs with a 10 MHz clock, 6.0 µs with a 12
MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs with a 20 MHz clock.
(9)
For Enhanced BC mode, the typical value for intermessage gap time
is approximately 10 clock cycles longer than for the non-enhanced
BC mode. That is, an addition of 1.0 µs at 10 MHz, 833 ns at 12
MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12)
θ
jc is measured to the bottom of the case.
(13) External 10 µF tantalum and 0.1 µF capacitors should be located as
close as possible to Pins 20 and 72, and a 0.1 µF at pin 37. The BU-
62864 should also have a 0.1 µF at pin 26.
(14) MIL-STD-1760 requires that the PCI Enhanced Mini-ACE produce a
20 Vp-p minimum output on the stub connection.
(15) Power dissipation specifications assume a transformer coupled con-
figuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
(7)
9.5
10.0
to
10.5
17.5
21.5
49.5
127
4
18.5
22.5
50.5
129.5
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
µs
µs
BC/RT/MT Response Timeout (Note 10)
•
18.5 nominal
•
22.5 nominal
•
50.5 nominal
•
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
THERMAL
72-Pin, Ceramic Flatpack / Gull Lead
Thermal Resistance, Junction-to-Case,
Hottest Die (θ
JC
) (Note 12)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
72-Pin, Ceramic Flatpack / Gull Lead
Size
Weight
TABLE 1 NOTES:
660.5
8.4
-55
-65
150
150
+300
°C/W
°C
°C
°C
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
0.6
(17)
in.
(mm)
oz
(g)
Notes 1 through 6 are applicable to the Receiver Differential Resistance and
Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins
TX/RX_A(B) and TX/RX_A(B) of the PCI Enhanced Mini-ACE hybrid.
(3)
(4)
It is assumed that all power and ground inputs to the hybrid are connected.
The specifications are applicable for both unpowered and powered
conditions.
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(16) The 5V tolerant pins are CLOCK_IN, RTAD0-5, RTAD_PAR,
RTAD_LAT, TXINH_A/B, and SSFLAG/EXT_TRIG.
(5)
Data Device Corporation
www.ddc-web.com
4
BU-62743/62843/62864
F-11/06-0
INTRODUCTION
The BU-62743 RT, and BU-62843/62864 BC/RT/MT PCI
Enhanced Mini-ACE family of MIL-STD-1553 terminals comprise
a complete integrated interface between a PCI host processor
and a MIL-STD-1553 bus. All members of the PCI Enhanced
Mini-ACE family are packaged in the same 1.0 square inch flat-
pack package. The PCI Enhanced Mini-ACE hybrids provide
footprint and software compatibility with the Enhanced Mini-ACE,
Mini-ACE (Plus) terminals, as well as software compatibility with
the older ACE series.
The PCI Enhanced Mini-ACE provides complete multiprotocol
support of MIL-STD-1553A/B/McAir and STANAG 3838. All ver-
sions integrate dual transceiver; along with protocol, host inter-
face, memory management logic; and a minimum of 4K words of
RAM. In addition, the BU-62864 BC/RT/MT terminals include
64K words of internal RAM, with built-in parity checking.
The PCI Enhanced Mini-ACEs include a 5V, voltage source
transceiver for improved line driving capability, with options for
MIL-STD-1760 and McAir compatibility. To provide further flexi-
bility, the PCI Enhanced Mini-ACE may operate with a choice of
10, 12, 16, or 20 MHz clock inputs.
The PCI Enhanced Mini-ACEs are fully compliant targets, as
defined by the PCI Local Bus Specification Revision 2.2, using a
32 bit interface that operates at clock speeds of up to 33 MHz,
from a 3.3V bus. The interface supports PCI interrupts and con-
tains a FIFO that handles PCI burst write transfer cycles. The
FIFO is deep enough to accept an entire 1553 message. The PCI
interface is NOT 5V tolerant and cannot be used in a 5V PCI sig-
naling environment. The PCI interface is powered by 3.3V.
The 64K RAM, in the 64K version, is powered by 5V.
One of the new salient features of the PCI Enhanced Mini-ACE
is its Enhanced Bus Controller architecture. The Enhanced BC's
highly autonomous message sequence control engine provides
a means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
The PCI Enhanced Mini-ACE RT offers the choice of single and
circular buffering for individual subaddresses. New enhance-
ments to the RT architecture include a global circular buffering
option for multiple (or all) receive subaddresses, a 50% rollover
interrupt for circular buffers, an interrupt status queue for logging
up to 32 interrupt events, and an option to automatically initialize
to RT mode with the Busy bit set. The interrupt status queue and
50% rollover interrupt features are also included as improve-
ments to the PCI Enhanced Mini-ACE's Monitor architecture.
Data Device Corporation
www.ddc-web.com
The PCI Enhanced Mini-ACE series terminals operate over the
full military temperature range of -55°C to +125°C. Available
screened to MIL-PRF-38534C, the terminals are ideal for military
and industrial processor-to-1553 applications.
TRANSCEIVERS
The transceivers in the PCI Enhanced Mini-ACE series terminals
are fully monolithic, requiring only a +5V power input. The trans-
mitters are voltage sources, which provide improved line driving
capability over current sources. This serves to improve perform-
ance on long buses with many taps. The transmitters also offer
an option which satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +5V-only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of higher terminal input impedance than is possible
for a 15 volt or 12 volt transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553 val-
idation test. This characteristic allows for longer cable lengths
between a system connector and the isolation transformers of an
embedded 1553 terminal.
To provide compatibility to McAir specs, the PCI Enhanced Mini-
ACE is available with an option for transmitters with increased
rise and fall times.
Additionally, for MIL-STD-1760 applications, the PCI Enhanced
Mini-ACE provides an option for a minimum stub voltage level of
20 volts peak-to-peak, transformer coupled.
The receiver sections of the PCI Enhanced Mini-ACE are fully
compliant with MIL-STD-1553B Notice 2 in terms of front-end
overvoltage protection, threshold, common mode rejection, and
word error rate.
PCI REGISTER AND MEMORY ADDRESSING
The PCI Interface contains a set of "Type 00h" PCI configuration
registers that are used to map the device into the host system.
There are two Base Address Registers that are used to imple-
ment ACE memory space (BAR0) and register space (BAR1).
The PCI configuration register space is mapped in accordance
with PCI revision 2.2 specifications.
The PCI Enhanced Mini-ACE acts as a target and responds to
the PCI commands listed in TABLE 2.
The PCI Enhanced Mini-ACE does NOT implement the Memory
Read Multiple, Memory Read Line or Memory Write and
Invalidate commands. However, in accordance with PCI rules,
the PCI Enhanced Mini-ACE will accept these requests and alias
them to the basic memory commands. For example, Memory
BU-62743/62843/62864
F-11/06-0
5
FPGA/CPLD
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