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SIT9365AC-2B2-25E74.250000E

产品描述LVDS Output Clock Oscillator,
产品类别无源元件    振荡器   
文件大小805KB,共16页
制造商SiTime
标准
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SIT9365AC-2B2-25E74.250000E概述

LVDS Output Clock Oscillator,

SIT9365AC-2B2-25E74.250000E规格参数

参数名称属性值
是否Rohs认证符合
Objectid7178011820
包装说明QFN, 6 PIN
Reach Compliance Codecompliant
Country Of OriginMalaysia, Taiwan, Thailand
YTEOL7.13
其他特性ENABLE/DISABLE FUNCTION; COMPLEMENTARY OPUTPUT
最长下降时间0.47 ns
频率调整-机械NO
频率稳定性25%
JESD-609代码e4
安装特点SURFACE MOUNT
端子数量6
标称工作频率74.25 MHz
最高工作温度70 °C
最低工作温度-20 °C
振荡器类型LVDS
输出负载100 OHM
封装等效代码SOLCC6,.1,43
物理尺寸3.2mm x 2.5mm x 0.9mm
最长上升时间0.47 ns
最大压摆率79 mA
最大供电电压2.75 V
最小供电电压2.25 V
标称供电电压2.5 V
表面贴装YES
最大对称度55/45 %
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)

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SiT9365
Description
Standard Frequency Ultra-low Jitter Differential Oscillator
Features
The
SiT9365
is a differential MEMS XO supporting
standard frequencies between 25 MHz and 325 MHz,
and engineered for low-jitter applications. Utilizing
SiTime’s unique DualMEMS
®
temperature sensing and
TurboCompensation
®
technology, the SiT9365 delivers
exceptional dynamic performance by providing
resistance to airflow, thermal gradients, shock and
vibration. This device also integrates multiple on-chip
regulators to filter power supply noise, eliminating the
need for a dedicated external LDO.
The SiT9365 can be factory programmed for specific
combinations of frequency, stability, voltage, and output
signaling. Programmability enables designers to optimize
clock configurations while eliminating long lead times and
customization costs associated with quartz devices
where each frequency is custom built.
Standard frequencies and programmability makes this
device ideal for telecom, networking, and industrial
applications that require a variety of frequencies and
operate in noisy environments.
Refer to
Manufacturing Notes
for proper reflow profile,
tape and reel dimension, and other manufacturing
related information.
32 standard frequencies from 25 MHz to 325 MHz
(For additional frequencies, refer to
SiT9366
and
SiT9367
datasheets)
LVPECL, Low-swing LVPECL, LVDS and HCSL output
signaling
0.1 ps RMS phase jitter (random) for Ethernet applications
Frequency stability as low as ±10 ppm
Wide temperature ranges from -40°C to 105°C
Industry-standard packages: 3.2 x 2.5 mm
2
, 7.0 x 5.0 mm
2
and 5.0 x 3.2 mm
2
package
Applications
10/40/100 Gbps Ethernet, SONET, SATA, SAS,
Fibre Channel
Telecom, networking, instrumentation, storage, servers
Block Diagram
Package Pinout
OE/NC
NC
GND
1
2
3
6
5
4
VDD
OUT-
OUT+
Figure 1. SiT9365 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 7
for Pin Descriptions)
Rev 1.1
20 July 2021
www.sitime.com
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