74LVC10A
Triple 3-input NAND gate
Rev. 5 — 17 November 2011
Product data sheet
1. General description
The 74LVC10A provides three 3-input NAND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC10AD
74LVC10ADB
74LVC10APW
74LVC10ABQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74LVC10A
Triple 3-input NAND gate
4. Functional diagram
1
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
2B
2C
3A
3B
3C
mna757
2
1Y
12
13
3
2Y
6
4
5
&
12
&
6
A
3Y
8
9
10
11
mna759
&
8
B
C
Y
mna758
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
74LVC10A
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
001aad047
74LVC10A
14 V
CC
13 1C
12 1Y
11 3C
10 3B
9
8
3A
3Y
terminal 1
index area
1B
2A
2B
2C
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 1C
12 1Y
11 3C
10 3B
9
3A
1A
1
001aad048
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO14 and (T)SSOP14
Fig 5.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A
1B, 2B, 3B
1C, 2C, 3C
Pin description
Pin
1, 3, 9
2, 4, 10
13, 5, 11
Description
data input
data input
data input
74LVC10A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 17 November 2011
2 of 14
NXP Semiconductors
74LVC10A
Triple 3-input NAND gate
Table 2.
Symbol
1Y, 2Y, 3Y
GND
V
CC
Pin description
…continued
Pin
12, 6, 8
7
14
Description
data outputs
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
X
H
[1]
Function selection
[1]
Output
nB
X
L
X
H
nC
X
X
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
50
100
-
500
+150
Unit
V
mA
V
mA
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
C
the value of P
D
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
C
the value of P
D
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
D
derates linearly with 4.5 mW/K.
74LVC10A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 17 November 2011
3 of 14
NXP Semiconductors
74LVC10A
Triple 3-input NAND gate
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
ambient temperature
input transition rise and fall
rate
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
40
0
0
Typ
-
-
-
-
-
-
Max
3.6
-
5.5
+125
20
10
Unit
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND
current
-
-
-
-
-
-
-
-
-
-
-
0.1
0.2
0.45
0.6
0.4
0.55
5
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
V
V
V
V
V
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
40 C
to +85
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.12
0.35
V
CC
0.7
0.8
40 C
to +125
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Max
-
-
-
-
0.12
0.7
0.8
V
V
V
V
V
V
V
Unit
0.35
V
CC
V
74LVC10A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 17 November 2011
4 of 14
NXP Semiconductors
74LVC10A
Triple 3-input NAND gate
Table 6.
Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
CC
I
CC
supply
current
additional
supply
current
input
capacitance
Conditions
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
-
-
40 C
to +85
C
Min
Typ
[1]
0.1
5
Max
10
500
40 C
to +125
C
Min
-
-
Max
40
5000
A
A
Unit
C
I
-
4.0
-
-
-
pF
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 7.
Symbol Parameter
t
pd
propagation delay
Conditions
nA, nB, nC to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
C
PD
power dissipation
capacitance
per gate; V
I
= GND to V
CC
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
[1]
[2]
[3]
[3]
[2]
40 C
to +85
C
Min
-
0.5
1.0
1.5
1.5
-
-
-
Typ
[1]
13
4.5
2.7
2.8
2.4
2.9
6.0
8.8
Max
-
11.2
6.3
6.7
5.7
-
-
-
40 C
to +125
C
Unit
Min
-
0.5
1.0
1.5
1.5
-
-
-
Max
-
12.9
7.4
7.8
6.6
-
-
-
ns
ns
ns
ns
ns
pF
pF
pF
Typical values are measured at T
amb
= 25
C
and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
t
pd
is the same as t
PLH
and t
PHL
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC2
f
o
) = sum of the outputs
74LVC10A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 17 November 2011
5 of 14
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