áç
DECEMBER 2004
XRT73R06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION
The XRT73R06 is a six channel fully integrated Line
Interface Unit (LIU) featuring EXAR’s R
3
Technology
(Reconfigurable, Relayless, Redundancy) for E3/
DS3/STS-1 applications. The LIU incorporates 6
independent Receivers, Transmitters and Jitter
Attenuators in a single 217 Lead BGA package.
Each channel of the XRT73R06 can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT73R06’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT73R06 provides a Parallel Microprocessor
Interface for programming and control.
The XRT73R06 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
•
E3/DS3 Access Equipment
•
DSLAMs
•
Digital Cross Connect Systems
•
CSU/DSU Equipment
•
Routers
•
Fiber Optic Terminals
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 73R06
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
RDY
INT
Pmode
RESET
XRT73R06
XRT73R06
µProcessor
Interface
CLKOUT_n
SFM_en
RLOL_n
E3Clk
DS3Clk
STS-Clk/12M
RxClk_n
RxPOS_n
RxNEG/LCV_n
Peak Detector
AGC/
Equalizer
Slicer
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
HDB3/
B3ZS
Decoder
RTIP_n
RRing_n
MUX
Local
LoopBack
Remote
LoopBack
RLOS_n
TxClk_n
TxPOS_n
TxNEG_n
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
Line
Driver
Tx
Pulse
Shaping
Tx
Control
Timing
Control
MUX
HDB3/
B3ZS
Encoder
Device
Monitor
TxON
Channel 0
Channel n...
Channel 5
ORDERING INFORMATION
P
ART
N
UMBER
XRT73R06IB
P
ACKAGE
217 Lead BGA
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
áç
FEATURES
RECEIVER
•
- 40°C to 85°C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
(Reconfigurable,
Relayless,
•
R
3
Technology
Redundancy)
input jitter tolerance
•
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
•
On chip Clock and Data Recovery circuit for high
•
Meets E3/DS3/STS-1 Jitter Tolerance Requirement
•
Detects and Clears LOS as per G.775
•
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
•
Integrated Pulse Shaping Circuit
•
Built-in B3ZS/HDB3 Encoder (which can be
disabled)
•
Accepts Transmit Clock with duty cycle of 30%-
70%
•
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
•
Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications
•
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
•
Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993
•
Provides low jitter output clock
TRANSMITTER
•
Generates pulses that comply with the STSX-1
Relayless,
pulse template, as specified in Bellcore GR-253-
CORE
•
R
3
Technology
Redundancy)
(Reconfigurable,
•
Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
•
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
•
Tri-state Transmit output capability for redundancy
applications
•
Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
•
Each Transmitter can be independently turned on
or off
•
Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
•
Transmitters provide Voltage Output Drive
CONTROL AND DIAGNOSTICS
•
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
•
Parallel Microprocessor Interface for control and
configuration
•
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
•
Supports
monitoring
optional
internal
Transmit
driver
•
Each channel supports Analog, Remote and Digital
Loop-backs
•
Declares Loss of Lock (LOL) Alarm
•
Built-in B3ZS/HDB3 Decoder (which can be
disabled)
•
Single 3.3 V ± 5% power supply
•
5 V Tolerant digital inputs
•
Available in 217 pin BGA Package
•
Recovered Data can be muted while the LOS
Condition is declared
•
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
2
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
F
IGURE
2. XRT73R06
IN
BGA
PACKAGE
(B
OTTOM
V
IEW
)
áç
XRT73R06
REV. 1.0.0
(See pin list for pin names and function)
A
B
C
D
E
F
G
H
J
K
L
XRT73R06
M
N
P
R
T
U
17
16
15
14
12
12
11
10
9
8
7
6
5
4
3
2
1
3
XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
áç
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
..............................................................................................................................................
Figure 1. Block Diagram of the XRT 73R06 ......................................................................................................
ORDERING INFORMATION ................................................................................................................... 1
F
EATURES
....................................................................................................................................................
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
......................................................................................................
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
........................................................................................................
Figure 2. XRT73R06 in BGA package (Bottom View) .......................................................................................
TABLE OF CONTENTS ...................................................................................................................................
1
1
2
2
2
3
1
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
A
NALOG
P
OWER AND
G
ROUND
................................................................................................................... 12
DIGITAL
P
OWER AND
G
ROUND
..................................................................................................................... 14
FUNCTIONAL DESCRIPTION ......................................................................................... 16
1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 16
1.1 N
ETWORK
A
RCHITECTURE
................................................................................................................................ 16
Figure 3. Network Redundancy Architecture ................................................................................................. 16
2.0 clock Synthesizer ............................................................................................................................. 17
2.1 C
LOCK
D
ISTRIBUTION
....................................................................................................................................... 17
Figure 5. Clock Distribution Congifured in E3 Mode Without Using SFM .......................................................
Figure 4. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor ..........................
3.0 The Transmitter Section ..................................................................................................................
Figure 6. Transmit Path Block Diagram ..........................................................................................................
17
17
19
19
3.1 T
RANSMIT
D
IGITAL
I
NPUT
I
NTERFACE
................................................................................................................ 19
Figure 7. Typical interface between terminal equipment and the XRT73R06 (dual-rail data) ......................... 19
Figure 8. Transmitter Terminal Input Timing ................................................................................................... 20
Figure 9. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ........................................... 20
3.2 T
RANSMIT
C
LOCK
............................................................................................................................................
3.3 B3ZS/HDB3 E
NCODER
....................................................................................................................................
3.3.1 B3ZS Encoding ...................................................................................................................................
3.3.2 HDB3 Encoding ..................................................................................................................................
21
21
21
21
Figure 10. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 21
Figure 11. B3ZS Encoding Format ................................................................................................................. 21
3.4 T
RANSMIT
P
ULSE
S
HAPER
................................................................................................................................ 22
Figure 13. Transmit Pulse Shape Test Circuit ................................................................................................ 22
3.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 22
Figure 12. HDB3 Encoding Format ................................................................................................................. 22
3.5 E3
LINE SIDE PARAMETERS
............................................................................................................................... 23
Figure 14. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ...................................................
T
ABLE
1: E3 T
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
...........................
Figure 15. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ..........
T
ABLE
2: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................
T
ABLE
3: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .
Figure 16. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................
T
ABLE
5: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) .....
T
ABLE
4: DS3 P
ULSE
M
ASK
E
QUATIONS
...........................................................................................................
23
24
25
25
26
26
27
27
3.6 T
RANSMIT
D
RIVE
M
ONITOR
............................................................................................................................... 28
3.7 T
RANSMITTER
S
ECTION
O
N
/O
FF
....................................................................................................................... 28
Figure 17. Transmit Driver Monitor set-up. ..................................................................................................... 28
4.0 The Receiver Section ....................................................................................................................... 30
1
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
áç
XRT73R06
REV. 1.0.0
Figure 18. Receive Path Block Diagram ......................................................................................................... 30
4.1 R
ECEIVE
L
INE
I
NTERFACE
................................................................................................................................ 30
Figure 19. Receive Line InterfaceConnection ................................................................................................ 30
4.2 A
DAPTIVE
G
AIN
C
ONTROL
(AGC) .................................................................................................................... 31
4.3 R
ECEIVE
E
QUALIZER
........................................................................................................................................ 31
Figure 20. ACG/Equalizer Block Diagram ...................................................................................................... 31
4.3.1 Recommendations for Equalizer Settings .......................................................................................
4.4 C
LOCK AND
D
ATA
R
ECOVERY
..........................................................................................................................
4.4.1 Data/Clock Recovery Mode ...............................................................................................................
4.4.2 Training Mode ....................................................................................................................................
4.5 LOS (L
OSS OF
S
IGNAL
) D
ETECTOR
..................................................................................................................
4.5.1 DS3/STS-1 LOS Condition .................................................................................................................
4.5.2 Disabling ALOS/DLOS Detection ......................................................................................................
31
31
31
31
32
32
32
T
ABLE
6: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION AND
C
LEARANCE
T
HRESHOLDS FOR A GIVEN SETTING OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 32
4.5.3 E3 LOS Condition: ............................................................................................................................. 33
Figure 21. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 33
Figure 22. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 33
4.5.4 Interference Tolerance ...................................................................................................................... 34
Figure 23. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 34
Figure 24. Interference Margin Test Set up for E3. ........................................................................................ 34
T
ABLE
7: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 35
4.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 36
4.6 B3ZS/HDB3 D
ECODER
................................................................................................................................... 36
Figure 25. Receiver Data output and code violation timing ............................................................................ 36
5.0 Jitter .................................................................................................................................................. 37
5.1 J
ITTER
T
OLERANCE
.......................................................................................................................................... 37
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 37
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 37
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 38
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 38
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 38
5.2 J
ITTER
T
RANSFER
............................................................................................................................................ 39
T
ABLE
8: J
ITTER
A
MPLITUDE VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ....................................... 39
T
ABLE
9: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
................................................................................. 39
T
ABLE
10: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 39
5.2.1 Jitter Generation ................................................................................................................................ 40
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 40
6.0 Diagnostic Features ......................................................................................................................... 41
6.1 PRBS G
ENERATOR AND
D
ETECTOR
................................................................................................................. 41
Figure 30. PRBS MODE ................................................................................................................................. 41
6.2 LOOPBACKS ................................................................................................................................................ 42
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 42
Figure 31. Analog Loopback ........................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 43
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 43
Figure 32. Digital Loopback ............................................................................................................................ 43
Figure 33. Remote Loopback ......................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 44
Figure 34. Transmit All Ones (TAOS) .............................................................................................................
7.0 Microprocessor interface Block .....................................................................................................
T
ABLE
11: S
ELECTING THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
......................................................................
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block ..................................................
44
46
46
46
7.1 T
HE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
S
IGNALS
........................................................................................ 47
T
ABLE
12: XRT73R06 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................ 47
7.2 A
SYNCHRONOUS AND
S
YNCHRONOUS
D
ESCRIPTION
......................................................................................... 48
T
ABLE
13: A
SYNCHRONOUS
T
IMING
S
PECIFICATIONS
......................................................................................... 49
2
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