TRANSISTOR OUTLINE PACKAGES
Q-TECH
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
Description
Q-Tech’s Transistor Outline package crystal oscillators
consist of a source clock square wave generator, logic
output buffers and/or logic divider stages, and a round A
T
high-precision quartz crystal built in an all metal TO
package.
Features
• Made in the USA
• ECCN: EAR99
• DFARS 252-225-7014 Compliant:
Electronic Component Exemption
• Wide frequency range from 0.045Hz to 125MHz
• Available as QPL MIL-PRF-55310/09 and/10 (TTL)
and /12 (CMOS)
• Choice of TO packages and pin outs
• Choice of supply voltages
• Choice of output logic options ( CMOS, ACMOS,
HCMOS, LVHCMOS, and TTL)
• A
T-Cut crystal
• All metal hermetically sealed package
• Tight or custom symmetry available
• Low height available
• External tuning capacitor option
• Fundamental and third overtone designs
• Tristate function option D
• Three-point crystal mounts
• Custom design available tailors to meet customer’s
needs
• Q-Tech does not use pure lead or pure tin in its
products
Ordering Information
Sample part number
Q T 1 AC D 5M - 2 0. 00 0 M Hz
Q T 1 AC D 5 M - 60.000MHz
Solder Dip Option:
T =
Standard
S = Solder Dip (*)
Package:
(See page 3)
Output Frequency
C
AC
HC
T
L
N
R
Z
Logic & Supply Voltage:
= CMOS +5.0V to +15.0V(**)
= ACMOS
+5.0V
= HCMOS
+5.0V
= TTL
+5.0V
= LVHCMOS
+3.3V
= LVHCMOS
+2.5V
= LVHCMOS
+1.8V
= Z output
Screening Option:
Blank = No Screening
M = Per MIL-PRF-55310, Level B
Frequency vs. Temperature Code:
1
= ± 100ppm at 0ºC to +70ºC
3(***) = ± 5ppm at 0ºC to +50ºC
4
= ± 50ppm at 0ºC to +70ºC
5
= ± 25ppm at -20ºC to +70ºC
6
= ± 50ppm at -55ºC to +105ºC
9
= ± 50ppm at -55ºC to +125ºC
10
= ± 100ppm at -55ºC to +125ºC
11
= ± 50ppm at -40ºC to +85ºC
12
= ± 100ppm at -40ºC to +85ºC
Tristate Option:
Blank = No Tristate
D = Tristate
(*) Hot Solder Dip Sn60/Pb40 per MIL-PRF 55310 is optional for an additional cost
(**) Please specify supply voltage when ordering CMOS
(***) Requires an external capacitor
For frequency stability vs. temperature options not listed herein, please request a
custom part number.
Applications
• Designed to meet today’s requirements for all voltage
applications
• Wide military clock applications
• Industrial controls
• Microcontroller driver
For Non-Standard requirements, contact Q-Tech Corporation at
Sales@Q-Tech.com
Packaging Options
• Standard packaging in black foam
Other Options Available For An Additional Charge
• P. I. N. D. test (MIL-STD 883, Method 2020)
• Lead trimming
All Transistor Outline packages are available in surface mount form.
Specifications subject to change without prior notice.
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Transistor Outline Packages (Revision F, March 2011) (ECO# 10145)
1
TRANSISTOR OUTLINE PACKAGES
Q-TECH
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
Electrical Characteristics
Parameters
QT1, 14
Output freq. range (Fo)
Supply voltage (Vdd)
Maximum Applied Voltage (Vdd max.)
Freq. stability (∆F/∆T)
Operating temp. (Topr)
Storage temp. (Tsto)
F and Vdd dependent
3 mA max. at 5V up to 5MHz
25 mA max. at 15V up to 15MHz
QT2
QT3
5V ~ 15Vdc ± 10%
-0.5 to +18Vdc
244Hz — 15MHz
C
AC
HC
732.4Hz — 85MHz
0.045Hz — 85MHz
732.4Hz — 85MHz
5.0Vdc ± 10%
-0.5 to +7.0Vdc
See Option codes
See Option codes
-62ºC to + 125ºC
20 mA max. -
25 mA max. -
35 mA max. -
45 mA max. -
0.045Hz ~ < 16MHz
16MHz ~ < 40MHz
40MHz ~ < 60MHz
60MHz ~
85MHz
T
L (*)
732.4Hz — 125MHz
0.045Hz — 85MHz
732.4Hz — 85MHz
3.3Vdc ± 10%
-0.5 to +5.0Vdc
Operating supply current
(Idd) (No Load)
3 mA max. - 0.045Hz ~ < 500kHz
6 mA max. - 500kHz ~ < 16MHz
10 mA max. - 16MHz ~ < 32MHz
20 mA max. - 32MHz ~ < 60MHz
30 mA max. - 60MHz ~ < 100MHz
40 mA max. - 100MHz ~ 125MHz
Symmetry
(50% of ouput waveform or 1.4Vdc for
TTL)
Rise and Fall times
(with typical load)
45/55% max. Fo < 4MHz
40/60% max. Fo ≥ 4MHz
30ns max.
(Measured from 10% to 90%)
15pF // 10kΩ
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
15ns max. Fo < 15kHz
6ns max. Fo 15kHz ~ 39.999MHz
3ns max. Fo 40MHz ~ 125 MHz
(Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL)
10TTL Fo < 20MHz
6TTL Fo ≥ 20MHz
10ms max.
0.9 x Vdd min.; 0.1 x Vdd max.
2.4V min.; 0.4V max.
±8 mA
VIH ≥ 2.2V Oscillation;
VIL ≤ 0.8V High Impedance
8ps typ. - < 40MHz
5ps typ. - ≥ 40MHz
-1.6mA / TTL
+40μA / TTL
0.9 x Vdd min.; 0.1 x Vdd max.
± 4mA .
VIH ≥ 0.7 x Vdd Oscillation;
VIL ≤ 0.3 x Vdd High Impedance
15ps typ. - < 40MHz
8ps typ. - ≥ 40MHz
15pF // 10kΩ
Output Load
Start-up time (Tstup)
Output voltage (Voh/Vol)
Output Current (Ioh/Iol)
Enable/Disable
Tristate function Pin 1
Jitter RMS 1σ (at 25ºC)
Aging (at 70ºC)
± 1mA typ. at 5V
± 6.8mA typ. at 15V
Call for details
± 24mA
± 5ppm max. first year / ± 2ppm typ. per year thereafter
(*)
Z
Available in 2.5Vdc (N) or 1.8Vdc (R)
Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf)
ECL, PECL, LVPECL are available. Please contact Q-Tech for details.
Q-TECH Corporation
-
10150 W. Jefferson Boulevard, Culver City 90232
-
Tel: 310-836-7900 - Fax: 310-836-2157
-
www.q-t e ch .co m
Transistor Outline Packages (Revision F, March 2011) (ECO# 10145)
2
TRANSISTOR OUTLINE PACKAGES
Q-TECH
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
Package Outline and Pin Connections
Dimensions are in inches (mm)
A
B
C
D
QT1
QT2
QT3
QT14
Q-TECH
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
D/C S/N
.260
(6.60)
.300
MAX.
.200
MAX.
(5.08)
(7.62)
MAX.
.175
(4.45)
.500
(12.70)
MIN.
.500
MIN.
(12.70)
.500
(12.70)
MIN.
.500 MIN.
(12.70)
.018
(.457)
.360
(9.14)
.018
(.457)
.018
(.457)
.540
.018
(.457)
.360
(9.14)
.500
(12.70)
PIN No. 1
PIN No. 1
(13.72)
PIN No. 1
PIN No. 1
.200
(5.08)
.300
(7.62)
.282
(7.16)
.200
(5.08)
.075
(1.91)
QT #
QT1
QT2
QT3
QT14
E/D
Conf Vcc GND Case Output or
N/C
A
B
C
D
8
12
8
8
4
6
4
4
4
6
4
4
5
5
5
5
3
3
3
3
Ext.
Cap
1&2
9 & 10
1&2
1&2
Equivalent
MIL-PRF-55310
Configuration
/09 = QT1T
/12 = QT1C
N/A
/10 = QT3T
/13 = QT3C
N/A
Package Information
• Package material (header and leads): Kovar
• Lead finish: Gold Plated – 50µ ~ 80µ inches
Nickel Underplate – 100µ ~ 250µ inches
• Cover: Pure Nickel Grade A
• Package to lid attachment: Resistance weld
• Weight: 2.0g typ., 4.96g max.
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Transistor Outline Packages (Revision F, March 2011) (ECO# 10145)
3
TRANSISTOR OUTLINE PACKAGES
Q-TECH
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
Test Circuit
TYPICAL TEST CIRCUIT FOR QT1T3 (10TTL)
+5VDC
0.01uF
OUTPUT
270
8
5
QT1T3
6k
1
2
4
D2
D1
Output Waveform (Typical)
SYMMETRY =
TH
T
Tr
VOH
Tf
Vdd
0.9xVdd
x 100%
0.5xVdd
20pF(*)
D3
D4
GND
0.1xVdd
VOL
TH
T
GND
Cext
D1-D4: 1N4148 or equivalent
(*) CL includes scope probe capacitance
Startup Time
Typical test circuit for TTL logic.
Vdd
TYPICAL SET-UP FOR START-UP TIME
RL
+
mA
-
+
Vdc
-
0.1µF
or
0.01µF
Vdd OUT
OUT
E/D GND
CL
Rs
Oscilloscope
54616B Agilent
Variable Ramp
+
POWER
SUPPLY
-
DUT
LOAD
6 TTL
10 TTL
CL(*)
12pF
20pF
RL
430Ω
270Ω
RS
10kΩ
6kΩ
Ts
Start-up box
(*) CL inclides the loading effect of the oscilloscope probe.
Supply Current
Typical test circuit for CMOS logic
TYPICAL SUPPLY CURRENT ICC (mA) AT 3.3Vdc & 5.0Vdc CMOS Logic NO LOAD
+ mA
+
Power
supply
-
+
Vdc
Vdd
0.1µF
or
E/D
0.01µF
Out
Output
45
40
GND
Icc (mA)
35
-
15pF
(*)
10k
Ground
30
25
20
15
10
5
0
0.5 2
8
16 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160
Freq(MHz)
Icc 3.3V
Icc 5V
Tristate Function
(*) CL includes probe and jig capacitance
The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it can
be left floating or tied to Vdd without deteriorating the electrical performance.
Frequency vs. Temperature Curve
40
30
20
Frequency Stability (PPM)
10
0
-10
-20
-30
-40
-50
-55
FREQUENCY STABILITY VERSUS TEMPERATURE QT1L -36MHz
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 105 110 115 120 125
Temperature (°C)
SN2
SN3
SN4
SN1
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Transistor Outline Packages (Revision F, March 2011) (ECO# 10145)
4
TRANSISTOR OUTLINE PACKAGES
Q-TECH
CORPORATION
TO-5 and TO-8 CRYSTAL CLOCK OSCILLATORS
1.8 to 15Vdc - 0.045Hz to 125MHz
Thermal Characteristics
The heat transfer model in a hybrid package is described in figure 1.
Heat spreading occurs when heat flows into a material layer of
increased cross-sectional area. It is adequate to assume that spreading
occurs at a 45° angle.
The total thermal resistance is calculated by summing the thermal
resistances of each material in the thermal path between the device
and hybrid case.
RT = R1 + R2 + R3 + R4 + R5
The total thermal resistance RT (see figure 2) between the heat source
(die) to the hybrid case is the Theta Junction to Case (Theta JC)
in°C/W.
• Theta junction to case (Theta JC) for this product is 30°C/W.
• Theta case to ambient (Theta CA) for this part is 100°C/W.
• Theta Junction to ambient (Theta JA) is 130°C/W.
Maximum power dissipation PD for this package at 25°C is:
• PD(max) = (TJ (max) – TA)/Theta JA
• With TJ = 175°C (Maximum junction temperature of die)
• PD(max) = (175 – 25)/130 = 1.15W
JA
JC
D/A epoxy
D/A epoxy
Die
45º
Heat
Hybrid Case
45º
Substrate
R1
R2
R3
R4
R5
Die
D/A epoxy
Substrate
D/A epoxy
Hybrid Case
(Figure 1)
T
CA
A
T
C
JC
T
J
Die
CA
(Figure 2)
Environmental Specifications
Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Transistor Outline packages. Q-Tech can also customize
screening and test procedures to meet your specific requirements. The Transistor Outline packages are designed and processed to exceed
the following test conditions:
Environmental Test
Temperature cycling
Constant acceleration
Seal: Fine and Gross Leak
Burn-in
Aging
Vibration sinusoidal
Shock, non operating
Thermal shock, non operating
Ambient pressure, non operating
Resistance to solder heat
Moisture resistance
Terminal strength
Resistance to solvents
Solderability
ESD Classification
Moisture Sensitivity Level
Test Conditions
MIL-STD-883, Method 1010, Cond. B
MIL-STD-883, Method 2001, Cond. A, Y1
MIL-STD-883, Method 1014, Cond. A and C
160 hours, 125°C with load
30 days, 70°C
MIL-STD-202, Method 204, Cond. D
MIL-STD-202, Method 213, Cond. I
MIL-STD-202, Method 107, Cond. B
MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum
MIL-STD-202, Method 210, Cond. C
MIL-STD-202, Method 106
MIL-STD-202, Method 211, Cond. C
MIL-STD-202, Method 215
MIL-STD-202, Method 208
MIL-STD-883, Method 3015, Class 1HBM 0 to 1,999V
J-STD-020, MSL=1
Please contact Q-Tech for higher shock requirements
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-te ch.com
Transistor Outline Packages (Revision F, March 2011) (ECO# 10145)
5
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