PL60203X
HCSL-Compatible Clock Generator for
PCI Express
General Description
The PL60203X is the smallest, high performance, lowest
power, 2 differential output clock IC available for HCSL
timing applications. PL60203X offers -130dBc at 10kHz
offset at 100MHz, with a very low jitter (2ps TIE RMS),
making it ideal for HCSL applications requiring small size
and low power.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
Input frequency:
Fundamental crystal or reference input: 25MHz.
Output frequency:
PL602031: 2 x 25MHz differential outputs.
PL602032: 2 x 100MHz differential outputs.
PL602033: 2 x 125MHz differential outputs.
PL602034: 2 x 200MHz differential outputs.
Very low jitter: 28ps peak-to-peak typical.
Very low phase noise:
-130dBc at 10kHz offset at 100MHz.
Compliant with PCI-Express Gen1, Gen2, and Gen3.
Power supply range: 2.25V to 3.63V.
Operating temperature range: -40°C to +85°C.
Available in 16-pin QFN, RoHS and PFOS compliant
package.
Block Diagram
Applications
Servers
Storage systems
Switches and routers
Gigabit Ethernet
Set-top boxes/DVRs
Ripple Blocker is a trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
December 11, 2013
Revision 1.1
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL60203X
Ordering Information
Part Number
(1)
Marking
602031
602031
602032
602032
602033
602033
602034
602034
Shipping
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Junction Temperature
Range
–40° to +85°C
–40° to +85°C
–40° to +85°C
–40° to +85°C
–40° to +85°C
–40° to +85°C
–40° to +85°C
–40° to +85°C
Package
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
16-Pin 3mm x 3mm QFN
PL602031UMG
PL602031UMG TR
PL602032UMG
PL602032UMG TR
PL602033UMG
PL602033UMG TR
PL602034UMG
PL602034UMG TR
Note:
1. The devices are RoHS and PFOS compliant.
December 11, 2013
2
Revision 1.1
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL60203X
Pin Configuration
16-Pin QFN (Top View)
Pin Description
Pin Number
1
2
3, 4
5
6, 7
10
11
12
15
16
8, 9
13, 14
Pin Name
XIN, FIN
GND0
CLK0[0:1]
VDD0
CLK1[0:1]
VDD1
OE1
GND1
XOUT
OE0
DNC
ePad
Pin Type
I
I
O
P
O
P
I
P
O
I
Pin Function
Crystal input pin or reference clock input.
GND connection for CLK0.
Differential clock output pair
VDD connection for CLK0
Differential clock output pair
VDD connection for CLK1
Output enable pin for CLK1. High=Enabled, Low=Disabled. OE1 has a
60KΩ pull-up resistor.
GND connection for CLK1
Crystal output pin
Output enable pin for CLK0. High=Enabled, Low=Disabled. OE0 has a
60KΩ pull-up resistor.
Do not connect.
Center pad for thermal relief. Connect to GND.
December 11, 2013
3
Revision 1.1
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL60203X
Absolute Maximum Ratings
(2)
Supply Voltage (V
IN
) .................................................... +4.6V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (T
S
) .......................................... 150°C
(3)
ESD Rating ............................................................... 2.0kV
Operating Ratings
(4)
Supply Voltage (V
IN
) ..................................... –0.5V to +4.6V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
(5)
Package Thermal Resistance
QFN Still-air (
JA
) ............................................... 60°C/W
QFN Junction-to-board (
JB
) ............................. 33°C/W
AC Electrical Characteristics
(6)
V
DD
= 3.3V
±
10% or 2.5V
±
10%, T
A
= -40°C to +85°C, HCSL termination applied.
Parameter
Crystal input frequency
Input (F
IN
) frequency
Input (F
IN
) signal amplitude
Internally AC coupled
PL602031
Output frequency
PL602032
PL602033
PL602034
Output enable time
Output disable time
Setting time
VDD sensitivity
Output rise time
Output fall time
Duty cycle
Period jitter, peak-to-peak
Phase jitter, RMS
0.9
25
100
125
200
10
10
10
-2
0.3
0.3
45
50
28
2.1
2
0.5
0.5
55
Condition
Fundamental crystal
Min.
Typ.
25
25
V
DD
Max.
Units
MHz
MHz
Vpp
MHz
MHz
MHz
MHz
ns
ns
ms
ppm
ns
ns
%
ps
ps
OE function, T
A
=25°C, add one clock period to this
measurement for a useable clock output.
OE function, T
A
=25
°
C
At power up (V
DD
≥ 2.25V)
Frequency vs. V
DD
±
10%, crystal input only.
20/80%
20/80%
At V
DD
/2
With capacitive decoupling between V
DD
and GND at 100MHz;
10,000 samples measured
For 10kHz to 10MHz integration range
DC Electrical Characteristics
(6)
V
DD
= 3.3V
±
10% or 2.5V
±
10%, T
A
= -40°C to +85°C, HCSL termination applied.
Symbol
I
DD
V
DD
V
OL
V
OH
Parameter
Supply current, dynamic
Operating voltage
Output low voltage
Output high voltage
HCSL termination,
(RS = 150
Ω
, RT = 49.9
Ω
) 3.3V
(RS = 100
Ω
, RT = 49.9
Ω
) 2.5V
Condition
At 100MHz, no load
2.25
Min.
Typ.
50
Max.
70
3.63
0.05
0.65
0.75
0.85
Units
mA
V
V
V
December 11, 2013
4
Revision 1.1
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL60203X
Crystal Characteristics
(6)
V
DD
= 3.3V ±10% or 2.5V ±10%, T
A
= -40°C to +85°C.
Symbol
F
XIN
C
L (XTAL)
Parameter
Fundamental crystal resonator
Crystal load rating
Maximum sustainable drive level
Operating drive level
C0
ESR
Notes:
2. Exceeding the absolute maximum ratings may damage the device.
3. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5k in series with 100pF.
4. The device is not guaranteed to function outside its operating ratings.
5. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
JA
and
JB
values
are determined for a 4-layer board in still-air number, unless otherwise stated.
6. Specification for packaged product only
Min.
Typ.
25
18
Max.
Units
MHz
pF
500
100
6
45
µW
µW
pF
Ω
Crystal shunt capacitance
Effective series resistance, fundamental
December 11, 2013
5
Revision 1.1
hbwhelp@micrel.com
or (408) 955-1690
FPGA/CPLD
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