Low Skew, 1-to-2 LVCMOS / LVTTL
Fanout Buffer W/ Complementary Output
8302I-01
Datasheet
D
ESCRIPTION
The 8302I-01 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout Buffer
w/Complementary Output. The 8302I-01 has a single ended clock
input. The single ended clock input accepts LVCMOS or LVTTL input
levels. The 8302I-01 is characterized at full 3.3V for input V
DD
, and
mixed 3.3V and 2.5V for output operating supply modes (V
DDO
).
Guaranteed output and part-to-part skew characteristics make the
8302I-01 ideal for clock distribution applications demanding well defi
ned performance and repeatability.
F
EATURES
• Complementary LVCMOS / LVTTL output
• LVCMOS / LVTTL clock input accepts LVCMOS or
LVTTL input levels
• Maximum output frequency: 250MHz
• Output skew: 165ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core/2.5V output supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free compliant package
B
LOCK
D
IAGRAM
Q
CLK
nQ
P
IN
A
SSIGNMENT
S
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q
GND
V
DDO
nQ
8302I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
©2017 Integrated Device Technology, Inc.
1
May 4, 2017
8302I-01 Datasheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
2
3
4,7
5
8
Name
V
DDO
V
DD
CLK
GND
nQ
Q
Power
Power
Input
Power
Output
Output
Pulldown
Type
Description
Output supply pins.
Power supply pin.
LVCMOS / LVTTL clock input.
Power supply ground.
Complementary clock output. LVCMOS / LVTTL interface levels.
Clock output. LVCMOS / LVTTL interface levels.
NOTE:
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
5
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
22
16
51
7
12
Maximum
Units
pF
pF
pF
kΩ
Ω
©2017 Integrated Device Technology, Inc.
2
May 4, 2017
8302I-01 Datasheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifi cations only. Functional operation of
product at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Charac-teristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
13
4
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.465, 50Ω to V
DDO
/2
V
OH
Output High Voltage
V
DDO
= 3.465, I
OH
= -100µA
V
DDO
= 2.625, 50Ω to V
DDO
/2
V
DDO
= 2.625, I
OH
= -100µA
V
DDO
= 3.465, 50Ω to V
DDO
/2
V
OL
Output Low Voltage
V
DDO
= 3.465, I
OL
= 100µA
V
DDO
= 2.625, 50Ω to V
DDO
/2
V
DDO
= 2.625, I
OL
= 100µA
-5
2.6
2.9
1.8
2.2
0.5
0.2
0.5
0.2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
V
V
V
V
V
V
V
V
©2017 Integrated Device Technology, Inc.
3
May 4, 2017
8302I-01 Datasheet
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
≤
133MHz
133MHz < ƒ
≤
250MHz
300
45
40
1.8
Test Conditions
Minimum
Typical
Maximum
250
2.7
165
800
800
55
60
Units
MHz
ns
ps
ps
ps
%
%
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
≤
133MHz
133MHz < ƒ
≤
250MHz
100
45
40
1.9
Test Conditions
Minimum
Typical
Maximum
250
2.9
250
900
850
55
60
Units
MHz
ns
ps
ps
ps
%
%
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2017 Integrated Device Technology, Inc.
4
May 4, 2017
8302I-01 Datasheet
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ROPAGATION
D
ELAY
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
©2017 Integrated Device Technology, Inc.
5
May 4, 2017
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