2:1 LVDS Multiplexer With 1:2 Fanout
and Internal Termination
G
ENERAL
D
ESCRIPTION
The 889474 is a high speed 2-to-1 differential multiplexer
with integrated 2 output LVDS fanout buffer and internal
termination and is a member of the family of high performance
clock solutions from IDT. The 889474 is optimized for
high speed and very low output skew, making it suitable
fo r u s e i n d e m a n d i n g a p p l i c a t i o n s s u c h a s S O N E T,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally
terminated differential input and V
REF
_
AC
pins allow other differential
signal families such as LVPECL, LVDS, LVHSTL and CML to be easily
interfaced to the input with minimal use of external components. The
889474 is packaged in a small 4mm x 4mm 24-pin VFQFN package
which makes it ideal for use in space-constrained applications.
889474
DATA SHEET
F
EATURES
•
Two differential LVDS outputs
•
INx, nINx pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, CML
•
50Ω internal input termination to V
T
•
Maximum output frequency: 2GHz (maximum)
•
Additive phase jitter, RMS: 0.06ps (typical)
•
Output skew: 20ps (maximum)
•
Propagation delay: 700ps (maximum)
•
2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free RoHS-complaint package
B
LOCK
D
IAGRAM
IN0
50Ω
P
IN
A
SSIGNMENT
V
REF
_
AC
1
nIN1
VT1
V
DD
V
T0
nIN0
V
REF_AC0
IN1
50Ω
50Ω
0
Q0
nQ0
V
DD
nIN0
Q1
V
REF
_
AC
0
VT0
IN0
V
DD
1
2
3
4
5
6
24 23 22 21 20 19
18
17
16
15
14
13
7
Q0
8
nQ0
9
V
DD
10
V
DD
11 12
Q1
nQ1
GND
GND
nc
SEL
GND
V
DD
MUX
V
T1
nIN1
V
REF_AC1
SEL
50Ω
1
nQ1
889474
24-Lead VFQFN
4mm x 4mm x 0.925mm package body
K Package
Top View
889474 REVISION A 11/11/15
1
©2015 Integrated Device Technology, Inc.
V
DD
IN1
889474 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6, 9, 10,
13, 19, 24
2, 20
3,
21
4, 22
5, 23
7, 8
11, 12
14, 17, 18
15
16
Name
V
DD
nIN0, nIN1
V
REF_AC0,
V
REF_AC1
V
T0,
V
T1
IN0, IN1
Q0, nQ0
Q1, nQ1
GND
SEL
nc
Power
Input
Output
Input
Input
Output
Output
Power
Input
Unused
Pullup
Type
Description
Positive supply pins.
Inverting differential clock inputs. 50Ω internal input termination to V
T
.
Reference voltage for AC-coupled applications.
Termination inputs.
Non-inverting differential clock inputs. 50Ω internal input termination to V
T
.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply ground.
Input select pin. LVCMOS/LVTTL interface levels.
No connect.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
25
Maximum
Units
kΩ
T
ABLE
3. T
RUTH
T
ABLE
Inputs
IN0
0
1
X
X
nIN0
1
0
X
X
IN1
X
X
0
1
nIN1
X
X
1
0
SEL
0
0
1
1
0
1
0
1
Outputs
Q0:Q1
nQ0:nQ1
1
0
1
0
2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT
AND INTERNAL TERMINATION
2
REVISION A 11/11/15
889474 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Input Current, INx, nINx
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
±50mA
±100mA
± 0.5mA
-40°C to +85°C
-65°C to 150°C
49.5°C/W (0 mps)
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
80
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
0
Typical
Maximum
V
DD
+ 0.3
0.7
5
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
R
IN
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
T_IN
V
REF_AC
Parameter
Input Resistance
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential
Input Voltage Swing
IN-to-V
T
Output Reference Voltage
IN-to-V
T
INx, nINx
INx, nINx
INx, nINx
INx, nINx
INx, nINx
INx, nINx
V
DD
– 1.4
V
DD
– 1.3
Test Conditions
IN-to-VT
Minimum
45
90
1.2
0
0.1
0.2
1.28
V
DD
– 1.2
Typical
50
100
Maximum
55
110
V
DD
V
IN
– 0.1
V
DD
Units
Ω
Ω
V
V
V
V
V
V
REVISION B 11/11/15
3
2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT
AND INTERNAL TERMINATION
889474 DATA SHEET
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
V
OUT
V
DIFF_OUT
V
OCM
Parameter
Output Voltage Swing
Differential Output Voltage Swing
Output Common Mode Voltage
Change in Common Mode Voltage
Test Conditions
Minimum
340
680
1.10
-50
Typical
400
800
1.35
50
Maximum
Units
mV
mV
V
mV
Δ
V
OCM
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
MUX_
ISOLATION
t
R
/t
F
Parameter
Output Frequency
Propagation Delay,
(Differential); NOTE 1
Q0:1/nQ0:1
IN-to-Q
SEL-to-Q
400
250
Condition
Minimum
Typical
Maximum
4
2
700
600
20
200
155.52MHz,
12kHz – 20MHz
0.06
55
20% to 80%
70
220
Units
Gpbs
GHz
ps
ps
ps
ps
ps
dB
ps
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
Refer to Additive Phase Jitter Section,
NOTE 5
Mux Isolation
Output Rise/Fall Time
NOTE: All parameters are characterized at
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Driving only one input clock.
2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT
AND INTERNAL TERMINATION
4
REVISION A 11/11/15
889474 DATA SHEET
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 155.52MHz
(12kHz to 20MHz)
= 0.06ps typical
SSB P
HASE
N
OISE
dBc/H
Z
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
REVISION B 11/11/15
5
2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT
AND INTERNAL TERMINATION
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
