Supertex inc.
Three Channel, Three Level, High Speed
Ultrasound Driver IC
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MD1716
Features
Advanced CMOS technology
4.5 to 12.5V power supply voltage
2.0A output source and sink current
6.5ns rise and fall time with 1.0nF load
10ns propagation delay
±2ns matched delay times
12 matched channels
1.8 to 3.3V CMOS logic interface
Smart logic threshold
Low inductance package
General Description
The Supertex MD1716, paired with the Supertex TC8020,
forms a three channel, three level, high voltage, high speed,
transmit pulser chip set. The chip set is designed for medical
ultrasound imaging applications but can also be used for
metal flaw detection, Non-Destructive Testing (NDT), and
piezoelectric transducer drivers.
The MD1716 is a three channel logic controller circuit with 12
low impedance MOSFET gate drivers. There are three sets of
control logic inputs, one each for channels A, B and C. Each
channel consists of two pairs of MOSFET gate drivers. These
drivers are designed to match the gate driving requirements
of the Supertex TC8020.
The TC8020 is the high voltage output stage of the pulser.
It consists of six pairs of MOSFETs. Each pair has both an
N- and P-channel MOSFET. They are designed to have the
same impedance and can provide typical peak currents of
±3.5 amps.
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Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Metal flaw detection
Non-Destructive Testing (NDT)
Typical Application Circuit
+3.3V
+12V
+12V
0 to +100V VPP
VLL/EN
AVDD
VDD
OP1A
ON1A
OP2A
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
SP6
GP1
GN1
GP2
GN2
GP3
GN3
GP6
GN6
GP5
GN5
GP4
GN4
SP4
SP2 SP5
SP3 SP1
DP1
DN1
DP2
DN2
DP3
TxA
POSA
NEGA
1.8 to 3.3V
CMOS
Input Logic
POSB
NEGB
POSC
NEGC
ON2A
OP1B
MD1716
ON1B
OP2B
ON2B
OP1C
ON1C
OP2C
ON2C
TC8020
DN3
DP6
DN6
DP5
DN5
DP4
SN3
DN4
SN1
TxB
TxC
AGND
GND
PAD SN6 SN4 SN2 SN5
VNN
0 to -100V
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
MD1716
Ordering Information
Package Option
Device
6.00x6.00mm body
1.00mm height (max)
0.50mm pitch
40-Lead QFN
MD1716
MD1716K6-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
GND and AGND, Ground
V
LL
logic input pin
AV
DD
1, V
DD
1, positive gate drive supply
V
DD
2, positive gate drive supply
Storage temperature
Power dissipation
Value
0V
-0.5V to +5.5V
-0.5V to +14.5V
-0.5V to +14.5V
-65°C to 150°C
1.3W
Pin Configuration
40
1
40-Lead QFN (K6)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect device
reliability. All voltages are referenced to device ground.
* 1.0oz 4-layer 3x4” PCB
Package Marking
MD1716K6
LLLLLLLLL
YYWW
AAA CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Package may or may not include the following marks: Si or
40-Lead QFN (K6)
Operating Supply Voltages
Sym
V
LL
AV
DD
V
DD
Parameter
Logic supply
Positive analog supply
Positive gate drive supply
Min
1.8
4.75
4.75
Typ
3.3
-
-
Max
3.6
12.9
12.9
Units Conditions
V
V
V
---
AV
DD
≥ V
DD
---
Operating Supply Current
Sym
I
VLL
I
AVDDQ
I
VDDQ
I
AVDDEN
I
VDDEN
I
AVDDCW
I
VDDCW
Parameter
Logic reference current
AV
DD
power down current
V
DD
power down current
AV
DD
power up current
V
DD
power up current
AV
DD
CW 5.0MHz current
V
DD
CW 5.0MHz current
(Over operating conditions unless otherwise specified, V
LL
= 3.3V, AV
DD
= V
DD
= +12V, T
A
= 25°C)
Min
-
-
-
-
-
-
-
Typ
10
400
50
2.0
0.7
10
33
Max
-
-
100
3.0
1.0
-
-
Units Conditions
µA
µA
mA
mA
mA
V
LL
= 3.3V
EN = 0, all inputs Low.
EN = 1, all inputs Low.
All channels on at 5.0MHz, No load.
V
DD
= 5.0V
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
2
Tel: 408-222-8888
www.supertex.com
MD1716
AC Electrical Characteristics
Sym
t
irf
t
r
t
f
t
dr
t
df
|t
r
- t
f
|
|t
dr
- t
df
|
t
dm
Δt
j
t
EN_ON
t
EN_OFF
Parameter
Input rise & fall time
Output rise time
Output fall time
Output rise delay
Output fall delay
Rise and fall time matching
Propagation delay matching
Delay time matching
Output jitter
IC enable time
IC disable time
(Over operating conditions unless otherwise specified, V
LL
= 3.3V, AV
DD
= V
DD
= +12V, T
A
= 25°C)
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
-
6.5
6.5
10
10
1.0
1.0
±2.0
20
-
-
Max
10
-
-
-
-
-
-
-
-
50
2.0
Units Conditions
ns
ns
ns
ns
ns
-
-
ns
ps
μs
μs
Logic input edge speed requirement
1.0nF load, see timing diagram,
input signal rise/fall time 2.0ns
1.0nF load, see timing diagram,
input signal rise/fall time 2.0ns
For each channel
Channel to Channel and Device to Device
V
DD
= 10V
---
---
P-Channel Gate Driver Outputs
Sym
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Sym
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Parameter
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
Min
-
-
1.7
1.7
Typ
-
-
2.0
2.0
Max
6.0
6.0
-
-
Units Conditions
Ω
Ω
A
A
I
SINK
= 100mA
I
SOURCE
= 100mA
---
---
N-Channel Gate Driver Outputs
Parameter
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
Min
-
-
1.7
1.7
Typ
3.0
4.0
2.0
2.0
Max
6.0
6.0
-
-
Units Conditions
Ω
Ω
A
A
I
SINK
= 100mA
I
SOURCE
= 100mA
---
---
Logic Inputs
Sym
V
ENL
V
IH
V
IL
I
IH
I
IL
Parameter
Chip disable low voltage
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Min
0
0.8V
LL
0
-
-1.0
Typ
-
-
-
-
-
Max
0.3
V
LL
0.2V
LL
1.0
-
Units Conditions
V
V
V
µA
µA
VLL/EN is a dual function pin
---
---
---
---
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
3
Tel: 408-222-8888
www.supertex.com
MD1716
Truth Table
EN
1
1
1
1
EN
1
1
1
1
EN
1
1
1
1
0
0→1
1→0
Logic Inputs A
POSA
0
0
1
1
NEGA
0
1
0
1
SP1
to
DP1
OFF
OFF
ON
OFF
SP3
to
DP3
OFF
OFF
ON
OFF
SP5
to
DP5
OFF
OFF
ON
OFF
OFF
SN1
to
DN1
OFF
ON
OFF
OFF
SN3
to
DN3
OFF
ON
OFF
OFF
SN5
to
DN5
OFF
ON
OFF
OFF
OFF
SP2
to
DP2
ON
OFF
OFF
OFF
SP6
to
DP6
ON
OFF
OFF
OFF
SP4
to
DP4
ON
OFF
OFF
OFF
OFF
SN2
to
DN2
ON
OFF
OFF
OFF
SN6
to
DN6
ON
OFF
OFF
OFF
SN4
to
DN4
ON
OFF
OFF
OFF
OFF
Logic Inputs B
POSB
0
0
1
1
NEGB
0
1
0
1
Logic Inputs C
POSC
0
0
1
1
X
0
0
NEGC
0
1
0
1
X
0
0
EN transitions from low to high or high to low should occur at all logic inputs low.
Timing Diagram
Input
t
dr
V
DD
90%
50%
50%
t
df
Output
0V
t
f
10%
t
r
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
4
Tel: 408-222-8888
www.supertex.com
MD1716
Detail Circuit
+12V
AVDD
+12V
VDD
V
DD
OP1A
GP1
DP1
V
DD
ON1A
GN1
SN1
SP2
GP2
DP2
V
DD
ON2A
GN2
SN2
MD1716
1 OF 3-CH
GND
PAD
TC8020
4 of 12-FETs
PAD
DN2
Load
TxA
DN1
V
NN
V
PP
SP1
VLL/EN
High Speed
Gate Buffers
V
DD
POSA
NEGA
AGND
Control
Logic
and
Level
Translation
OP2A
Circuit Pin Layout
VSUB
GP2
GP1
SN2
SN1
SP1
SP2
NC
NC
NC
NC
NC
NC
ON1A
ON2A
OP1A
OP2A
GND
GND
VDD
VDD
VDD
VDD
GN1
GN2
ON1B
GND
VDD
OP1B
NC
GN3
GP3
NC
SN3
SN6
NC
GP6
GN6
NC
GN5
GN4
NC
SN5
NC
SN4
NC
VSUB
GP5
GP4
NC
SP4
NC
SP5
NC
NC
NC
DN1
DP1
DN2
DP2
DN3
DP3
POSA
NEGA
POSB
VLL/EN
AVDD
AGND
AGND
NEGB
POSC
NEGC
OP1B
GND
OP2B
ON1B
GND
ON2B
VDD2
VDD1
VDD2
VDD1
TxA
MD1716
GND
VDD
OP2B
GND
ON2B
GND
TC8020
SP3
SP6
DN6
DP6
DN5
DP5
DN4
DP4
TxB
TxC
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
5
Tel: 408-222-8888
www.supertex.com
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