MR25H256
FEATURES
•
No write delays
•
Unlimited write endurance
•
Data retention greater than 20 years
•
Automatic data protection on power loss
•
Block write protection
•
Fast, simple SPI interface with up to 40 MHz clock rate
•
2.7 to 3.6 Volt power supply range
•
Low current sleep mode
•
Industrial temperatures
•
Available in 8-pin DFN or 8-pin DFN Small Flag RoHS-compliant pack-
ages.
•
Direct replacement for serial EEPROM, Flash, FeRAM
•
AEC-Q100 Grade 1 option
256Kb Serial SPI MRAM
DFN
Small Flag DFN
INTRODUCTION
The
MR25H256
is a 262,144-bit magnetoresistive random access memory (MRAM) device orga-
nized as 32,768 words of 8 bits. The
MR25H256
offers serial EEPROM and serial
Flash compatible read/write timing with no write delays and unlimited read/write
endurance.
RoHS
Unlike other serial memories, both reads and writes can occur randomly in memo-
ry with no delay between writes. The
MR25H256
is the ideal memory solution for applications that must
store and retrieve data and programs quickly using a small number of I/O pins.
The
MR25H256
is available in either a 5 mm x 6 mm 8-pin DFN package or a 5 mm x 6 mm 8-pin DFN
Small Flag package. Both are compatible with serial EEPROM, Flash, and FeRAM products.
The
MR25H256
provides highly reliable data storage over a wide range of temperatures. The product is
offered with industrial (-40° to +85 °C) and AEC-Q100 Grade 1 (-40°C to +125 °C) operating temperature
range options.
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 3
2. SPI COMMUNICATIONS PROTOCOL...................................................... 4
3. ELECTRICAL SPECIFICATIONS................................................................. 10
4. TIMING SPECIFICATIONS.......................................................................... 14
5. ORDERING INFORMATION....................................................................... 16
6. MECHANICAL DRAWING.......................................................................... 17
7. REVISION HISTORY...................................................................................... 18
How to Reach Us.......................................................................................... 18
Copyright © Everspin Technologies 2013
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MR25H256 Rev. 9, 4/2013
MR25H256
1. DEVICE PIN ASSIGNMENT
Overview
The MR25H256 is a serial MRAM with memory array logically organized as 32Kx8 using the four pin interface
of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral interface
(SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash com-
ponents allowing MRAM to replace these components in the same socket and interoperate on a shared SPI
bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and
more reliable data retention compared to available serial memory alternatives.
Figure 1.1 Block Diagram
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
32KB
MRAM ARRAY
Instruction Register
Address Register
Counter
SI
15
8
SO
Data I/O Register
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 1.2 System Configuration
SCK
MOSI
MISO
SO
SPI
Micro Controller
SI
SCK
SO
SI
SCK
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
CS
CS
1
HOLD
1
CS
2
HOLD
2
HOLD
CS
HOLD
MOSI = Master Out Slave In
MISO = Master In Slave Out
Copyright © Everspin Technologies 2013
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MR25H256 Rev. 9, 4/2013
MR25H256
DEVICE PIN ASSIGNMENT
Figure 1.3 Pin Diagrams (Top View)
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
DD
HOLD
SCK
SI
8-Pin DFN or 8-Pin DFN Small Flag Packages
Table 1.1 Pin Functions
Signal Name Pin
CS
1
I/O
Input
Function
Chip Select
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
A low on the write protect input prevents write operations to the Status
Register.
Power supply ground pin.
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
Power supply voltage from +2.7 to +3.6 volts.
SO
2
Output
Serial Output
WP
V
SS
SI
3
4
5
Input
Supply
Input
Write Protect
Ground
Serial Input
SCK
6
Input
Serial Clock
HOLD
7
Input
Hold
V
DD
8
Supply
Power Supply
Copyright © Everspin Technologies 2013
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MR25H256 Rev. 9, 4/2013
MR25H256
2. SPI COMMUNICATIONS PROTOCOL
MR25H256 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).
For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The
memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS
falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code. De-
pending upon the command, subsequent bytes of address are input. Data is either input or output. There
is only one command performed per CS active period. CS must go inactive before another command can
be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each
access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or
aborted accesses.
Table 2.1 Command Codes
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
SLEEP
WAKE
Description
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
Binary Code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1011 1001
1010 1011
Hex Code
06h
04h
05h
01h
03h
02h
B9h
ABh
Address Bytes
0
0
0
0
2
2
0
0
Data Bytes
0
0
1
1
1 to ∞
1 to ∞
0
0
Status Register and Block Write Protection
The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 define the mem-
ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD)
is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable
writes to status register bits. The fast writing speed of MR25H256 does not require write status bits. The
state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status
register are pre-set from the factory to the “0” state.
Table 2.2 Status Register Bit Assignments
Bit 7
SRWD
Bit 6
Don’t Care
Bit 5
Don’t Care
Bit 4
Don’t Care
Bit 3
BP1
Bit 2
BP0
Bit 1
WEL
Bit 0
Don’t Care
Copyright © Everspin Technologies 2013
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MR25H256 Rev. 9, 4/2013
MR25H256
SPI COMMUNICATIONS PROTOCOL
Table 2.3 Block Memory Write Protection
Status Register
BP1
BP0
0
0
0
1
1
0
1
1
Memory Contents
Protected Area
None
Upper Quarter
Upper Half
All
Table 2.4 Memory Protection Modes
WEL
0
1
1
1
SRWD
X
0
1
1
WP
X
X
Low
High
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Writable
Writable
Status
Register
Protected
Writable
Protected
Writable
Unprotected Area
All Memory
Lower Three-Quarters
Lower Half
None
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1,
BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,
status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD,
BP0 and BP1.
Read Status Register (RDSR)
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can
be read at any time to check the status of write enable latch bit, status register write protect bit, and block
write protect bits. For MR25H256, the write in progress bit (bit 0) is not written by the memory because
there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and
then driving CS high.
CS
0
1
2
3
4
5
Figure 2.1 RDSR
6
7
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
SI
SO
0
0
0
0
0
1
0
1
MSB
Status Register Out
High Impedance
7
MSB
6
5
4
3
2
1
0
High Z
Copyright © Everspin Technologies 2013
5
MR25H256 Rev. 9, 4/2013
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