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T8535A---ML-D: 产品描述Programmable Codec, A/MU-Law, 4-Func, PQCC44, PLASTIC, LCC-44; 产品类别无线/射频/通信电信电路; 文件大小1MB，共50页; 制造商AVAGO; 官网地址http://www.avagotech.com/

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T8535A---ML-D概述

Programmable Codec, A/MU-Law, 4-Func, PQCC44, PLASTIC, LCC-44

T8535A---ML-D规格参数

参数名称	属性值
是否无铅	含铅
厂商名称	AVAGO
零件包装代码	LCC
包装说明	,
针数	44
Reach Compliance Code	unknown
压伸定律	A/MU-LAW
滤波器	NO
JESD-30 代码	S-PQCC-J44
功能数量	4
端子数量	44
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装形状	SQUARE
封装形式	CHIP CARRIER
认证状态	Not Qualified
标称供电电压	5 V
表面贴装	YES
电信集成电路类型	PROGRAMMABLE CODEC
温度等级	INDUSTRIAL
端子形式	J BEND
端子位置	QUAD
Base Number Matches	1

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Preliminary Data Sheet

September 2000

T8535A/T8536A Quad Programmable Codec

Features

Description

The device consists of four independent channels of

codec and digital signal processing functions on one

chip. In addition to the classic A-to-D and D-to-A con-

version, each channel provides termination imped-

ance synthesis and a hybrid balance network.

The device is controlled by a serial microprocessor

interface, and a series of bidirectional I/O leads are

provided so that this control mechanism can be uti-

lized to operate the battery feed device, ringing volt-

age switches, etc. Common data and clock paths can

be shared over any number of devices. All the filter

coefficients, signal processing, SLIC, and test fea-

tures are accessible through this interface. This

serial interface can be operated at speeds up to

16 Mbits/s.

The choice of a PCM bus is also programmable, with

any channel capable of being assigned to any time

slot. The PCM bus can be operated at speeds up to

16.384 Mbits/s, allowing for a maximum of 256 time

slots. Separate transmit and receive interfaces are

available for 4-wire bus designs, or they can be

strapped together for a 2-wire PCM bus.

The device is available in four packages.

The T8536A 64-pin TQFP features five data latches

per channel and has two PCM ports.

The T8536A 100-pin TQFP features six data latches

per channel and has two PCM ports.

The T8536A 68-pin PLCC features six data latches

per channel and has one PCM port.

The T8535A 44-pin PLCC has no data latches and

one PCM port.

The T8535A and the T8533 Quad Programmable

Line Card Signal Processor with Echo Cancellation

are pin compatible, as are the T8536A 68-pin PLCC

device and the T8534 68-pin PLCC Quad Program-

mable Line Card Signal Processor with Echo Cancel-

lation.

5 V operation

Per-channel programmable gains, equalization,

termination impedance, and hybrid balance

Programmable

µ-law,

linear, or A-law modes

— Up to 256 time slots per frame

— Supports PCM data rates of 512 kbits/s to

16.384 Mbits/s

— Double-clock mode timing compatible with

ISDN standard interfaces

Fully programmable time-slot assignment with bit

offset

Analog and digital loopback test modes

Serial microprocessor interface

— Normal and byte-by-byte control modes

— Fast scan mode

Six bidirectional control leads per channel, for

SLIC and line card function control

Differential analog output

— Mates directly to SLICs, eliminating external

components

Sigma-delta converters with dither noise reduction

Quad design to minimize package count on dense

line card applications

Meets or exceeds ITU-T G.711—G.712 and rele-

vant

Telcordia Technologies

* requirements

Telcordia Technologies

is a trademark of Bell Communications

Research, Inc.

T8535A/T8536A Quad Programmable Codec

Preliminary Data Sheet

September 2000

Table of Contents

Contents

Page

Features .................................................................................................................................................................... 1

Description.................................................................................................................................................................1

General Description................................................................................................................................................... 5

Pin Information ..........................................................................................................................................................7

Functional Description .............................................................................................................................................15

Clocking Considerations .......................................................................................................................................15

The Control Interface ............................................................................................................................................15

Modes ................................................................................................................................................................15

Protocol ..............................................................................................................................................................16

Write Command .................................................................................................................................................18

Read Command .................................................................................................................................................20

Fast Scan Mode .................................................................................................................................................22

Write All Channels..............................................................................................................................................24

Reset Functionality ...............................................................................................................................................24

Memory Control Mapping ...................................................................................................................................25

Standby Mode.......................................................................................................................................................25

Test Capabilities ...................................................................................................................................................25

SLIC Control Capabilities ......................................................................................................................................25

Suggested Initialization Procedures......................................................................................................................26

Signal Processing .................................................................................................................................................26

Absolute Maximum Ratings.....................................................................................................................................27

Operating Ranges ...................................................................................................................................................27

Handling Precautions ..............................................................................................................................................27

Electrical Characteristics .........................................................................................................................................28

dc Characteristics .................................................................................................................................................28

Analog Interface....................................................................................................................................................29

Gain and Dynamic Range .....................................................................................................................................30

Noise Characteristics ............................................................................................................................................32

Distortion and Group Delay...................................................................................................................................33

Crosstalk ...............................................................................................................................................................34

Timing Characteristics .............................................................................................................................................35

Control Interface Timing........................................................................................................................................35

Serial Control Port Timing ..................................................................................................................................35

Normal Mode......................................................................................................................................................36

Byte-by-Byte Mode.............................................................................................................................................36

PCM Interface Timing ...........................................................................................................................................37

Single-Clocking Mode ........................................................................................................................................37

Double-Clocking Mode.......................................................................................................................................39

Software Interface ...................................................................................................................................................41

Applications .............................................................................................................................................................45

Outline Diagrams.....................................................................................................................................................46

100-Pin TQFP .......................................................................................................................................................46

68-Pin PLCC .........................................................................................................................................................47

64-Pin TQFP .........................................................................................................................................................48

44-Pin PLCC .........................................................................................................................................................49

Ordering Information................................................................................................................................................50

Lucent Technologies Inc.

Preliminary Data Sheet

September 2000

T8535A/T8536A Quad Programmable Codec

Table of Contents

(continued)

Figures

Page

Figure 1. Functional Block Diagram, Each Section...................................................................................................5

Figure 2. 44-Pin PLCC Pin Diagram .........................................................................................................................7

Figure 3. 68-Pin PLCC Pin Diagram .........................................................................................................................9

Figure 4. 100-Pin TQFP Pin Diagram .....................................................................................................................11

Figure 5. 64-Pin TQFP Pin Diagram .......................................................................................................................13

Figure 6. Command Frame Format, Master to Slave, Read or Write Commands ..................................................17

Figure 7. Command Frame Format, Slave to Master, Read Commands................................................................17

Figure 8. Write Operation, Normal Mode (Continuous DCLK) ................................................................................18

Figure 9. Write Operation, Byte-by-Byte Mode (Gapped DCLK) ............................................................................18

Figure 10. Write Operation, Byte-by-Byte Mode (Continuous DCLK) .....................................................................19

Figure 11. Read Operation, Normal Mode (Continuous DCLK) ..............................................................................20

Figure 12. Read Operation, Byte-by-Byte Mode (Gapped Clock) ...........................................................................21

Figure 13. Read Operation, Byte-by-Byte Mode (Continuous DCLK) .....................................................................21

Figure 14. Fast Scan, Normal Mode (Continuous DCLK) .......................................................................................22

Figure 15. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) ...................................................................................23

Figure 16. Fast Scan, Byte-by-Byte Mode (Continuous DCLK) ..............................................................................23

Figure 17. Hardware Reset Procedure ...................................................................................................................24

Figure 18. Internal Signal Processing .....................................................................................................................26

Figure 19. Serial Interface Timing, Normal Mode (One Byte Transfer and Continuous DCLK Shown) ..................36

Figure 20. Byte-by-Byte Mode Timing (Gapped DCLK Shown) ..............................................................................36

Figure 21. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00) ......................................38

Figure 22. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01) ......................................38

Figure 23. Double-Clocking Mode (Bit Offset = 0, PCMCTRL2 = 0x00) .................................................................40

Figure 24. POTS Interface ......................................................................................................................................45

Lucent Technologies Inc.

T8535A/T8536A Quad Programmable Codec

Preliminary Data Sheet

September 2000

Table of Contents

(continued)

Tables

Page

Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions ........................................................................... 7

Table 2. Pin Assignments, 44-Pin PLCC, Common Functions................................................................................. 8

Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions ........................................................................... 9

Table 4. Pin Assignments, 68-Pin PLCC, Common Functions............................................................................... 10

Table 5. Pin Assignments, 100-Pin TQFP, Per-Channel Functions ....................................................................... 11

Table 6. Pin Assignments, 100-Pin TQFP, Common Functions............................................................................. 12

Table 7. Pin Assignments, 64-Pin TQFP, Per-Channel Functions ......................................................................... 13

Table 8. Pin Assignments, 64-Pin TQFP, Common Functions............................................................................... 14

Table 9. Bit Assignments for Fast Scan Mode ....................................................................................................... 22

Table 10. dc Characteristics ................................................................................................................................... 28

Table 11. Analog Interface ..................................................................................................................................... 29

Table 12. Power Dissipation................................................................................................................................... 29

Table 13. Gain and Dynamic Range ...................................................................................................................... 30

Table 14. Per-Channel Noise Characteristics ........................................................................................................ 32

Table 15. Distortion and Group Delay .................................................................................................................... 33

Table 16. Crosstalk................................................................................................................................................. 34

Table 17. Serial Control Port Timing ...................................................................................................................... 35

Table 18. PCM Interface Timing: Single-Clocking Mode........................................................................................ 37

Table 19. PCM Interface Timing: Double-Clocking Mode ...................................................................................... 39

Table 20. Memory Mapping.................................................................................................................................... 41

Table 21. Control Bit Definition............................................................................................................................... 42

Lucent Technologies Inc.

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