ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ V
DD1
= V
DDA
≤ 5.5 V; V
DD2
= V
REG
= V
ISO
= 5.0 V; f
SW
= 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DDA
= 5.0 V, V
DD2
= V
REG
= V
ISO
= 5.0 V.
Table 1.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Isolated Output Voltage
Feedback Voltage Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Symbol
V
ISO
V
FB
V
ISO (LINE)
V
ISO (LOAD)
V
ISO (RIP)
V
ISO (N)
f
SW
192
Switch On Resistance
Undervoltage Lockout, V
DD1
, V
DD2
Supplies
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 2 Mbps Data Rate
1
Maximum Output Supply Current
2
Efficiency at Maximum Output
Supply Current
3
iCOUPLER
DATA CHANNELS
DC to 2 Mbps Data Rate
1
I
DD1
Supply Current, No V
ISO
Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
25 Mbps Data Rate (C Grade Only)
I
DD1
Supply Current, No V
ISO
Load
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
Available V
ISO
Supply Current
4
ADuM3470
ADuM3471
ADuM3472
ADuM3473
ADuM3474
I
DD1
Supply Current, Full V
ISO
Load
R
ON
Min
4.5
1.125
Typ
5.0
1.25
1
1
50
100
1000
200
318
0.5
Max
5.5
1.375
10
2
Unit
V
V
mV/V
%
mV p-p
mV p-p
kHz
kHz
kHz
Ω
Test Conditions/Comments
I
ISO
= 0 mA, V
ISO
= V
FB
× (R1 + R2)/R2
I
ISO
= 0 mA
I
ISO
= 50 mA, V
DD1
= 4.5 V to 5.5 V
I
ISO
= 50 mA to 200 mA
20 MHz bandwidth,
C
OUT
= 0.1 µF||47 µF, I
ISO
= 100 mA
20 MHz bandwidth,
C
OUT
= 0.1 µF||47 µF, I
ISO
= 100 mA
R
OC
= 50 kΩ
R
OC
= 270 kΩ
V
OC
= V
DD2
(open loop)
515
V
UV+
V
UV−
V
UVH
I
ISO (MAX)
400
2.8
2.6
0.2
V
V
V
mA
%
f ≤ 1 MHz
V
ISO
= 5.0 V
I
ISO
= I
ISO (MAX)
70
I
DD1 (Q)
14
15
16
17
18
I
DD1 (D)
44
46
48
50
52
I
ISO (LOAD)
390
388
386
384
382
550
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
30
30
30
30
30
mA
mA
mA
mA
mA
I
ISO
= 0 mA, f ≤ 1 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
I
DD1 (MAX)
C
L
= 0 pF, f = 0 MHz, V
DD1
= 5 V,
I
ISO
= 400 mA
Rev. B | Page 3 of 36
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Parameter
I/O Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Symbol
I
IA
, I
IB
, I
IC
, I
ID
V
IH
V
IL
V
OAH
, V
OBH
,
V
OCH
, V
ODH
Min
−20
2.0
V
DD1
− 0.3,
V
ISO
− 0.3
V
DD1
− 0.5,
V
ISO
− 0.5
Typ
+0.01
Max
+20
0.8
5.0
4.8
0.0
0.0
AC SPECIFICATIONS
A Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Propagation Delay Skew
Channel-to-Channel Matching
C Grade
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
At Logic High Output
At Logic Low Output
Refresh Rate
1
2
Data Sheet
Unit
µA
V
V
V
V
Test Conditions/Comments
I
Ox
= −20 µA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
C
L
= 15 pF, CMOS signal levels
Logic Low Output Voltages
V
OAL
, V
OBL
,
V
OCL
, V
ODL
0.1
0.4
V
V
PW
1
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
/t
PSKOD
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
t
R
/t
F
25
30
45
5
55
1000
100
40
50
50
40
60
8
15
8
15
2.5
ns
Mbps
ns
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
|CM
H
|
|CM
L
|
f
r
25
25
35
35
1.0
kV/µs
kV/µs
Mbps
C
L
= 15 pF, CMOS signal levels
V
CM
= 1000 V, transient
magnitude = 800 V
V
Ix
= V
DD1
or V
ISO
V
Ix
= 0 V
The contributions of supply current values for all four channels are combined at identical data rates.
The V
ISO
supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the V
ISO
power budget.
3
The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the V
ISO
output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
Rev. B | Page 4 of 36
Data Sheet
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V ≤ V
DD1
= V
DDA
≤ 3.6 V; V
DD2
= V
REG
= V
ISO
= 3.3 V; f
SW
= 500 kHz; all voltages are relative to their respective grounds (see the
application schematic in Figure 38). All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at T
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
