organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location addressed
by the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
Temperature Ranges
❐
Commercial: 0°C to 70°C
❐
Industrial: –40°C to 85°C
❐
Automotive-A: –40°C to 85°C
❐
Automotive-E: –40°C to 125°C
High Speed: 55 ns
Voltage Range: 4.5V to 5.5V Operation
Low Active Power
❐
275 mW (max)
Low Standby Power (LL version)
❐
82.5
μW
(max)
Easy Memory Expansion with CE and OE Features
TTL-Compatible Inputs and Outputs
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
Available in Pb-free and Non Pb-free 28-Pin (600-mil) PDIP,
28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin
Reverse TSOP-I Packages
■
■
■
■
■
■
■
■
■
Logic Block Diagram
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
CE
WE
OE
A
14
A
13
A
12
A
11
A
1
A
0
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
32K x 8
Y
ARRA
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note
1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com
Cypress Semiconductor Corporation
Document #: 001-06511 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 03, 2009
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CY62256N
Product Portfolio
Product
CY62256NL
CY62256NLL
CY62256NLL
CY62256NLL
CY62256NLL
Commercial /
Industrial
Commercial
Industrial
Automotive-A
Automotive-E
Min
4.5
V
CC
Range (V)
Typ
[2]
5.0
Max
5.5
Speed
(ns)
70
70
55/70
55/70
55
Power Dissipation
Operating, I
CC
Standby, I
SB2
(μA)
(mA)
Typ
[2]
Max
Typ
[2]
Max
25
50
2
50
25
25
25
25
50
50
50
50
0.1
0.1
0.1
0.1
5
10
10
15
Pin Configurations
Figure 1. 28-Pin DIP and Narrow SOIC
Figure 2. 28-Pin TSOP I and Reverse TSOP I
Table 1. Pin Definitions
Pin Number
1–10, 21, 23–26
11–13, 15–19,
27
20
22
14
28
Type
Input
Input/Output
Input/Control
Input/Control
Input/Control
Ground
Power Supply
Description
A
0
–A
14
. Address Inputs
I/O
0
–I/O
7
. Data lines. Used as input or output lines depending on operation
WE.
When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
CE.
When LOW, selects the chip. When HIGH, deselects the chip
OE.
Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input
data pins
GND.
Ground for the device
V
CC
. Power supply for the device
Note
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (T
A
= 25°C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 001-06511 Rev. *B
Page 2 of 14
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CY62256N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. -55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)............................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[3]
.................................... –0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
................................ –0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Latch up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Automotive-A
Automotive-E
Ambient Temperature (T
A
)
[4]
0
°
C to +70
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
L-Commercial/
Industrial
LL-Commercial
LL - Industrial
LL - Auto-A
LL - Auto-E
I
SB1
Automatic CE
Power down Current—
TTL Inputs
Max. V
CC
, CE > V
IH
, L
V
IN
> V
IH
or V
IN
< V
IL
, LL-Commercial
f = f
MAX
LL - Industrial
LL - Auto-A
LL - Auto-E
I
SB2
Automatic CE
Power down Current—
CMOS Inputs
Max. V
CC
,
L
CE > V
CC
−
0.3V
LL-Commercial
V
IN
> V
CC
−
0.3V, or
LL - Industrial
V
IN
< 0.3V, f = 0
LL - Auto-A
LL - Auto-E
25
25
25
50
50
50
0.4
0.3
0.3
0.3
0.3
0.5
0.5
0.5
2
0.1
0.1
0.1
0.1
10
10
15
0.1
0.1
50
5
10
10
0.3
0.3
0.6
0.5
0.5
0.5
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
Test Conditions
V
CC
= Min., I
OH
=
−1.0
mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
–0.5
–0.5
–0.5
-55
Min
2.4
0.4
V
CC
+0.5V
0.8
+0.5
+0.5
2.2
–0.5
–0.5
–0.5
25
25
25
25
Typ
[2]
Max
Min
2.4
0.4
V
CC
+0.5V
0.8
+0.5
+0.5
50
50
50
50
-70
Typ
[2]
Max
Unit
V
V
V
V
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
[5]
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
Notes
3. V
IL
(min.) =
−
2.0V for pulse durations of less than 20 ns.
4. T
A
is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06511 Rev. *B
Page 3 of 14
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CY62256N
Thermal Resistance
Parameter
Θ
JA
Θ
JC
Description
[5]
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 4.25 x 1.125
inch, 4-layer printed circuit board
DIP
75.61
43.12
SOIC
76.56
36.07
TSOP
93.89
24.64
RTSOP
93.89
24.64
Unit
°C/W
°C/W
Figure 3. AC Test Loads and Waveforms
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
990Ω
R1 1800Ω
R1 1800Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
990Ω
3.0V
GND
10%
ALL INPUT PULSES
90%
90%
10%
< 5 ns
< 5 ns
(a)
(b)
Equivalent to:
THÉ
VENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
L
LL-Commercial
LL - Industrial/Auto-A
LL - Auto-E
t
CDR[8]
t
R
[8]
Conditions
[6]
V
CC
= 2.0V, CE > V
CC
−
0.3V,
V
IN
> V
CC
−
0.3V, or V
IN
< 0.3V
Min
2.0
Typ
[2]
2
0.1
0.1
0.1
Max
50
5
10
10
Unit
V
μA
μA
μA
μA
ns
ns
Chip Deselect to Data Retention Time
Operation Recovery Time
0
t
RC
Figure 4. Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
3.0V
t
CDR
V
DR
> 2V
3.0V
t
R
Note
6. No input may exceed V
CC
+ 0.5V.
Document #: 001-06511 Rev. *B
Page 4 of 14
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CY62256N
Switching Characteristics
Over the Operating Range
[7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
Description
CY62256N-55
Min
55
55
5
55
25
5
20
5
20
0
55
55
45
45
0
0
40
25
0
20
5
5
0
5
5
5
Max
CY62256N-70
Min
70
70
70
35
25
25
70
70
60
60
0
0
50
30
0
25
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Power up
CE HIGH to Power down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to Low-Z
[8]
Write Cycle
[10, 11]
Switching Waveforms
Figure 5. Read Cycle No. 1
[12, 13]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Notes
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
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