32MB / 64MB / 128MB (x 64)
168-PIN SDRAM DIMMs
SYNCHRONOUS
DRAM MODULE
FEATURES
• PC100- and PC133-compliant
• JEDEC-standard, 168-pin, dual in-line memory
module (DIMM)
• Utilizes 100 MHz and 133 MHz SDRAM compo-
nents
• Unbuffered
• 32MB (4 Meg x 64), 64MB (8 Meg x 64), 128MB (16
Meg x 64)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 32, 64MB: 4ms, 4,096-cycle refresh; 128MB: 4ms,
8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
MT4LSDT464A - 32MB
MT4LSDT864A - 64MB
MT4LSDT1664A- 128MB
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/dramds
168-Pin DIMM
MO-161
TIMING PARAMETERS
MODULE
MARKING
-13E
-133
-10E
PC133
(CL -
t
RCD -
t
RP)
2-2-2
3-3-3
n/a
PC100
(CL -
t
RCD -
t
RP)
2-2-2
2-2-2
2-2-2
PART NUMBERS
PART NUMBER
CONFIGURATION SYSTEM BUS SPEED
MT4LSDT464AG-13E_
4 Meg x 64
133 MHz
MT4LSDT464AG-133_
4 Meg x 64
133 MHz
MT4LSDT464AG-10E_
4 Meg x 64
100 MHz
MT4LSDT864AG-13E_
8 Meg x 64
133 MHz
MT4LSDT864AG-133_
8 Meg x 64
133 MHz
MT4LSDT864AG-10E_
8 Meg x 64
100 MHz
MT4LSDT1664AG-13E_
16 Meg x 64
133 MHz
MT4LSDT1664AG-133_
16 Meg x 64
133 MHz
MT4LSDT1664AG-10E_
16 Meg x 64
100 MHz
NOTE:
The designators for component and PCB revision are
the last two characters of each part number. Consult
factory for current revision codes. Example:
MT4LSDT1664AG-133B1.
OPTIONS
• Package
168-pin DIMM (gold)
MARKING
G
• Frequency/CAS Latency
133 MHz/CL = 2 (7.5ns, 133 MHz SDRAM)
133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs)
100 MHz/CL = 2 (8ns, 100 MHz SDRAMs)
-13E
-133
-10E
ADDRESS TABLE
32MB
Module
Refresh Count
4K
Device Banks
4 (BA0, BA1)
Device Configuration 4 Meg x 16
Row Addressing
4K (A0–A11)
Column Addressing
256 (A0–A7)
Module Banks
1 (S0, S2)
64MB
Module
4K
4 (BA0, BA1)
8 Meg x 16
4K (A0–A11)
512 (A0–A8)
1 (S0, S2)
128MB
Module
8K
4 (BA0, BA1)
16 Meg x 16
8K (A0–A12)
512 (A0–A8)
1 (S0, S2)
4, 8,16 Meg x 64 SDRAM DIMMs
sd4c4_8_16x64a_a – Rev. 10/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
32MB / 64MB / 128MB (x 64)
168-PIN SDRAM DIMMs
PIN ASSIGNMENT (168-PIN DIMM FRONT)
PIN SYMBOL PIN SYMBOL
1
V
SS
22
DNU
2
DQ0
23
V
SS
3
DQ1
24
NC
4
DQ2
25
NC
5
DQ3
26
V
DD
6
V
DD
27
WE#
7
DQ4
28
DQM0
8
DQ5
29
DQM1
9
DQ6
30
S0#
10
DQ7
31
NC
11
DQ8
32
V
SS
12
V
SS
33
A0
13
DQ9
34
A2
14
DQ10
35
A4
15
DQ11
36
A6
16
DQ12
37
A8
17
DQ13
38
A10
18
V
DD
39
BA1
19
DQ14
40
V
DD
20
DQ15
41
V
DD
21
DNU
42
CKO
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
SYMBOL
V
SS
NC
S2#
DQM2
DQM3
NC
V
DD
NC
NC
DNU
DNU
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
CKE1
PIN
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
PIN ASSIGNMENT (168-Pin DIMM BACK)
PIN SYMBOL PIN SYMBOL PIN
85
V
SS
106
DNU
127
86
DQ32
107
V
SS
128
87
DQ33
108
NC
129
88
DQ34
109
NC
130
89
DQ35
110
V
DD
131
90
V
DD
111
CAS#
132
91
DQ36
112 DQM4
133
92
DQ37
113 DQM5
134
93
DQ38
114
DNU
135
94
DQ39
115
RAS#
136
95
DQ40
116
V
SS
137
96
V
SS
117
A1
138
97
DQ41
118
A3
139
98
DQ42
119
A5
140
99
DQ43
120
A7
141
100
DQ44
121
A9
142
101
DQ45
122
BA0
143
102
V
DD
123
A11
144
103
DQ46
124
V
DD
145
104
DQ47
125
DNU
146
105
DNU
126 NC/A12* 147
SYMBOL
V
SS
CKE0
DNU
DQM6
DQM7
DNU
V
DD
NC
NC
DNU
DNU
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
NC
PIN
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
DNU
NC
SA0
SA1
SA2
V
DD
*Pin 126 is NC for 32MB and 64MB modules, or A12 for 128MB module.
Front View
U1
U2
U4
U5
U6
PIN 1
PIN 84
Back View
No Components on This Side of Module
PIN 168
PIN 85
4, 8,16 Meg x 64 SDRAM DIMMs
sd4c4_8_16x64a_a – Rev. 10/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
32MB / 64MB / 128MB (x 64)
168-PIN SDRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
27, 111, 115
42, 79
SYMBOL
RAS#, CAS#,
WE#
CK0, CK2
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with
S0#, S2#) define the command being entered.
Clock: CK0, CK2 are driven by the system clock. All
SDRAM input signals are sampled on the positive edge
of CK. CK also increments the internal burst counter
and controls the output registers.
Clock Enable: CKE0 activates (HIGH) and deactivates
(LOW) the CK0, CK2 signals. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all device banks idle), ACTIVE
POWER-DOWN (row ACTIVE in any device bank), or
CLOCK SUSPEND operation (burst access in progress).
CKE0 is synchronous except after the device enters
power-down and self refresh modes, where CKE0
becomes asynchronous until after exiting the same
mode. The input buffers, including CK0, CK2 are
disabled during power-down and self refresh modes,
providing low standby power.
Chip Select: S0# and S2# enable (registered LOW) and
disable (registered HIGH) the command decoder. All
commands are masked when S0# and S2# are registered
HIGH. S0# and S2# are considered part of the command
code.
Input/Output Mask: DQM is an input mask signal for
write accesses and an output enable signal for read
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when
DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device
bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address Inputs: A0-A11/A12 are sampled during the
ACTIVE command (row-address A0-A11, 32MB/64MB;
A0-A12, 128MB) and READ/WRITE command (column-
address A0-A7, 32MB; A0-A8, 64MB/128MB with A10
defining auto precharge) to select one location out of
the memory array in the respective device bank. A10 is
sampled during a PRECHARGE command to determine
if all device banks are to be precharged (A10 HIGH) or
device bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE
REGISTER command.
Write Protect: Serial presence-detect hardware write
protect.
128
CKE0
Input
30, 45
S0#, S2#
Input
28, 29, 46, 47,
112, 113, 130, 131
DQM0-DQM7
Input
39, 122
BA0, BA1
Input
33-38, 117-121, 123
126(128MB)
A0-A11
(32MB/64MB)
A0-A12
(128MB)
Input
81
WP
Input
NOTE:
Pin numbers are listed in module pinout order and do not necessarily correlate with symbols.
4, 8,16 Meg x 64 SDRAM DIMMs
sd4c4_8_16x64a_a – Rev. 10/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
32MB / 64MB / 128MB (x 64)
168-PIN SDRAM DIMMs
PIN DESCRIPTIONS (continued)
PIN NUMBERS
83
SYMBOL
SCL
TYPE
Input
DESCRIPTION
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
Data I/Os: Data bus.
165-167
82
SA0-SA2
SDA
Input
Input/
Output
Input/
Output
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95,
97-101, 103-104, 139-142,
144, 149-151, 153-156,
158-161
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
21, 22, 52, 53, 105, 106,
114, 125, 129, 132, 136,
137, 163
24, 25, 31, 44, 48, 50, 51,
61, 62, 80, 108,109,
126(32MB/64MB), 134,
135, 145-147, 164
DQ0-DQ63
V
DD
Supply
Power Supply: +3.3V ±0.3V.
V
SS
Supply
Ground.
DNU
–
Do Not Use: These pins are not used on these
module, but are assigned pins on other modules in
this product family.
Not Connected: These pins are not connected on these
module.
NC
–
NOTE:
Pin numbers are listed in module pinout order and do not necessarily correlate with symbols.
4, 8,16 Meg x 64 SDRAM DIMMs
sd4c4_8_16x64a_a – Rev. 10/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
32MB / 64MB / 128MB (x 64)
168-PIN SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
All Modules
S0#
DQM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
S2#
DQM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM2
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
RAS#
CAS#
CKE0
WE#
A0-A11(32MB/64MB)
A0-A12(128MB)
BA0-1
V
DD
V
SS
DQML CS#
DQ0
U4
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML CS#
DQ0
U1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQML CS#
DQ0
U2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM3
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQML CS#
DQ0
U5
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U1
U2
RAS#: SDRAMs U1, U2, U4, U5
CAS#: SDRAMs U1, U2, U4, U5
CKE: SDRAMs U1, U2, U4, U5
WE#: SDRAMs U1, U2, U4, U5
A0-A11: SDRAMs U1, U2, U4, U5
A0-A12: SDRAMs U1, U2, U4, U5
BA0-1: SDRAMs U1, U2, U4, U5
SDRAMs U1, U2, U4, U5
SDRAMs U1, U2, U4, U5
SPD
CK0
11.2pF
CK2
U4
U5
13.6pF
CK1,CK3
10pF
SCL
WP
A0
U6
A1
A2
SDA
U1,U2,U4,U5 = MT48LC4M16A2TG SDRAMs for 32MB
U1,U2,U4,U5 = MT48LC8M16A2TG SDRAMs for 64MB
U1,U2,U4,U5 = MT48LC16M16A2TG SDRAMs for 128MB
SA0 SA1 SA2
NOTE:
Unless otherwise indicated, all resistor values are 10 ohms.
4, 8,16 Meg x 64 SDRAM DIMMs
sd4c4_8_16x64a_a – Rev. 10/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
