.
Preliminary
Features
IBM0418A80QLAB IBM0436A80QLAB
IBM0418A40QLAB IBM0436A40QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
• 256K x 36 or 512K x 18 Organizations
• 128K x 36 or 256K x 18 Organizations
• 0.25 Micron CMOS Technology
• Synchronous Flow Thru Mode of Operation with
Self-Timed Late Write
• Differential HSTL Input Clocks (K, K)
• Differential HSTL Output Clocks (C, C)
• +3.3V Power Supply, Ground, 1.6V V
DDQ
, and
0.95V V
REF
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins.
• Common I/O
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability & Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
Scan Order
• Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAM
S
are Synchronous
Flowthru Mode, high-performance CMOS Static
Random Access Memories that are versatile and
wide I/O, and can achieve 3ns cycle times. Differen-
tial K clocks are used to initiate the read/write opera-
tion and all internal operations are self-timed. At the
rising edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Differential clocks C and C are used to
control the Output Data hold time by allowing output
data to change after the rising edge of the C clock.
An internal Write buffer allows write data to follow
one cycle after addresses and controls. The chip is
operated with a single +3.3V power supply and is
compatible with HSTL I/O interface.
cfth3316.01
7/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 5
IBM0418A80QLAB IBM0436A80QLAB
IBM0418A40QLAB IBM0436A40QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ19
DQ22
V
DDQ
DQ24
DQ25
V
DDQ
DQ34
DQ33
V
DDQ
DQ31
DQ28
NC
NC
V
DDQ
2
SA
NC
SA
DQ18
DQ20
DQ21
DQ23
DQ26
V
DD
DQ35
DQ32
DQ30
DQ29
DQ27
SA
NC
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWc
V
SS
V
REF
V
SS
SBWd
V
SS
V
SS
V
SS
M1*
SA
TDI
4
NC
NC
V
DD
ZQ
SS
G
C
C
V
DD
K
K
SW
SA
SA
V
DD
SA
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
V
REF
V
SS
SBWa
V
SS
V
SS
V
SS
M2*
SA
TDO
6
SA
NC,SA(8Mb)
SA
DQ9
DQ11
DQ12
DQ14
DQ17
V
DD
DQ8
DQ5
DQ3
DQ2
DQ0
SA
NC
NC
7
V
DDQ
NC
NC
DQ10
DQb13
V
DDQ
DQb15
DQb16
V
DDQ
DQ7
DQ6
V
DDQ
DQ4
DQ1
NC
ZZ
V
DDQ
Note:
* M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
DD
.
x18 BGA Pinout
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ14
NC
V
DDQ
NC
DQ17
V
DDQ
NC
DQ12
V
DDQ
DQ11
NC
NC
NC
V
DDQ
(Top View)
2
SA
NC
SA
NC
DQ15
NC
DQ16
NC
V
DD
DQ13
NC
DQ10
NC
DQ9
SA
SA
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
V
REF
V
SS
NC
V
SS
V
SS
V
SS
M1
SA
TDI
4
NC
NC
V
DD
ZQ
SS
G
C
C
V
DD
K
K
SW
SA
SA
V
DD
NC
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
NC
V
SS
V
REF
V
SS
SBWa
V
SS
V
SS
V
SS
M2
SA
TDO
6
SA
NC,SA(8Mb)
SA
DQ0
NC
DQ2
NC
DQ4
V
DD
NC
DQ7
NC
DQ6
NC
SA
SA
NC
7
V
DDQ
NC
NC
NC
DQ1
V
DDQ
DQ3
NC
V
DDQ
DQ8
NC
V
DDQ
NC
DQ5
NC
ZZ
V
DDQ
Note:
* M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
DD
.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
cfth3316.01
7/99
Page 2 of 5
Preliminary
IBM0418A80QLAB IBM0436A80QLAB
IBM0418A40QLAB IBM0436A40QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Input
SA0-SA18 for 512Kx18
SA0-SA17 for 256Kx36
SA0-SA17 for 256Kx18
SA0-SA16 for 128Kx36
Data I/O
DQ0-DQ17 for 512Kx18
DQ0-DQ35 for 256Kx36
Differential Input Register Clocks
Differential Output Data Hold Control Clocks
Write Enable, Global
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE 1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
SA0-SA18
G
Asynchronous Output Enable
DQ0-DQ35
SS
Synchronous Select
K, K
C,C
SW
SBWa
SBWb
SBWc
SBWd
TMS,TDI,TCK
TDO
M1, M2
V
REF
(2)
V
DD
V
SS
V
DDQ
ZZ
ZQ
NC
Clock Mode Inputs.
HSTL Input Reference Voltage
Power Supply (+3.3V)
Ground
Output Power Supply
Asynchronous Sleep Mode
Output Driver Impedance Control
No Connect
Ordering Information
(These are all possible sorts; some may not be qualified.)
Part Number
IBM0418A40QLAB - 3T
IBM0418A40QLAB - 3S
IBM0418A40QLAB - 3E
IBM0418A40QLAB - 4T
IBM0436A40QLAB - 3T
IBM0436A40QLAB - 3S
IBM0436A40QLAB - 3E
IBM0436A40QLAB - 4T
IBM0418A80QLAB - 3T
IBM0418A80QLAB - 3S
IBM0418A80QLAB - 3E
IBM0418A80QLAB - 4T
IBM0436A80QLAB -3T
IBM0436A80QLAB -3S
IBM0436A80QLAB -3E
IBM0436A80QLAB -4T
256K x 36
512K x 18
128K x 36
256K x 18
Organization
Speed
4.2ns Access / 3.3ns Cycle
4.5ns Access / 3.6ns Cycle
5.0ns Access /3.8ns Cycle
5.5ns Access /4.2ns Cycle
4.2ns Access / 3.3ns Cycle
4.5ns Access / 3.6ns Cycle
5.0ns Access /3.8ns Cycle
5.5ns Access /4.2ns Cycle
4.2ns Access / 3.3ns Cycle
4.5ns Access / 3.6ns Cycle
5.0ns Access /3.8ns Cycle
5.5ns Access /4.2ns Cycle
4.2ns Access / 3.3ns Cycle
4.5ns Access / 3.6ns Cycle
5.0ns Access /3.8ns Cycle
5.5ns Access /4.2ns Cycle
7 x 17 BGA
Leads
cfth3316.01
7/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 5
IBM0418A80QLAB IBM0436A80QLAB
IBM0418A40QLAB IBM0436A40QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Revision Log
Revision
11/98
7/99
Initial release.
Corrected BGA Dimension on page 28
Contents of Modification
For a complete datasheet, please contact your IBM sale representative.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
cfth3316.01
7/99
Page 4 of 5
®
©
Intern
ational Business Machines Corp.1999
Copyright
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
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