K6F2008U2E Family
Document Title
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
1.0
2.0
Initial Draft
Finalize
Revise
- Added 48(36)-TBGA-6.00x7.00 products.
Draft Date
February 28, 2001
Remark
Preliminary
September 27, 2001 Final
April 30, 2002
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
April 2002
K6F2008U2E Family
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
• Process Technology: Full CMOS
• Organization: 256Kx8
• Power Supply Voltage: 2.7~3.3V
• Low Data Retention Voltage: 1.5V(Min)
• Three State Outputs
• Package Type: 32-TSOP1-0813.4F, 48(36)-TBGA-6.00x7.00
CMOS SRAM
GENERAL DESCRIPTION
The K6F2008U2E families are fabricated by SAMSUNG′s
advanced Full CMOS process technology. The families support
various operating temperature ranges and have various pack-
age types for user flexibility of system design. The families also
supports low data retention voltage for battery back-up opera-
tion with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed(ns)
Standby
(I
SB1
, Typ.)
0.5µA
2)
Operating
(I
CC1
, Max)
2mA
PKG Type
K6F2008U2E-F
Industrial(-40~85°C)
2.7~3.3V
55
1)
/70ns
32-TSOP1-0813.4F
48(36)-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
2. Typical values are measured at V
CC
=3.0V, T
A
=25°C and not 100% tested.
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
FUNCTIONAL BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5
6
Address
32-sTSOP
Type1-Forward
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
I/O
1
I/O
8
Clk gen.
Precharge circuit.
Row
select
Memory array
1024 rows
256x8 columns
3
4
Data
cont
I/O Circuit
Column select
A
A
0
I/O
5
I/O
6
V
SS
A
1
A
2
CS
2
WE
DNU
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
I/O
2
V
CC
Data
cont
B
C
Address
D
48(36)-TBGA
E
V
CC
I/O
7
I/O
8
A
9
OE
A
10
DNU
CS
1
A
11
A
17
A
16
A
12
A
15
A
13
V
SS
I/O
3
I/O
4
A
14
F
CS1
CS2
WE
OE
Control
logic
G
Name
Function
Name
Function
H
CS
1
, CS
2
Chip Select Input
OE
WE
Output Enable
Write Enable Input
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Vss
Power
Ground
A
0
~A
17
Address Inputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 2.0
April 2002
K6F2008U2E Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F2008U2E-YF55
K6F2008U2E-YF70
K6F2008U2E-EF55
K6F2008U2E-EF70
Function
CMOS SRAM
32-sTSOP1-F, 55ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
48(36)-TBGA, 55ns, 3.0V, LL
48(36)-TBGA, 70ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disable
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don
′
t care (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to V
CC
+0.3V
-0.2 to 3.6V
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
April 2002
K6F2008U2E Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
2.7
0
2.2
-0.2
3)
Typ
3.0
0
-
-
CMOS SRAM
Max
3.3
0
Vcc+0.2
2)
0.6
Unit
V
V
V
Note:
1. Industrial Product: T
A
=-40 to 85°C, unless otherwise specified
2. Overshoot: Vcc+2.0V in case of pulse width≤20ns
3. Undershoot: -2.0V in case of pulse width≤20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Symbol
I
LI
I
LO
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(CMOS)
V
OL
V
OH
I
SB1
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
,
CS
2
=V
IH
, V
IN
=V
IL
or V
IH
I
OL
=2.1mA
I
OH
=-1.0mA
Other inputs=Vss to Vcc
1) CS
1
≥Vcc-0.2V,
CS2≥Vcc-0.2V(CS
1
controlled) or
2) 0V≤CS
2
≤0.2V
CS
2
controlled)
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL,
V
IO
=Vss to Vcc
Cycle time=1µs, 100% duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥V
CC
-0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
70ns
55ns
Test Conditions
Min
-1
-1
-
-
-
-
2.4
-
Typ
1)
-
-
-
-
-
-
-
0.5
Max
1
1
2
15
20
0.4
-
10
Unit
µA
µA
mA
mA
mA
V
V
µA
1. Typical value are measured at V
CC
=3.0V, T
A
=25°C, and not 100% tested.
4
Revision 2.0
April 2002
K6F2008U2E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM3)
R
12)
C
L1)
R
23)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=2.7~3.3V, Industrial product: T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Read
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
1. The parameter is measured with 30pF test load.
55ns
1)
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
20
-
-
-
Units
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-0.2V
1)
Vcc=1.5V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
t
RC
Typ
2)
-
0.5
-
-
Max
3.3
2
-
-
Unit
V
µA
ns
1. 1) CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or
2) 0≤CS
2
≤0.2V(CS
2
controlled).
2. Typical value are measured at T
A
=25°C and not 100% tested.
5
Revision 2.0
April 2002
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