PRELIMINARY
‡
128Mb: x16
GRAPHICAL DDR SDRAM ADDENDUM
DOUBLE DATA RATE
(DDR) SDRAM
Features
• 200 MHz Clock, 400 Mb/s/p data rate
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
•
t
RAS lockout (
t
RAP =
t
RCD)
• Single CAS Latency CL=3
Options
• Configuration
8 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package
66-Pin TSOP (400 mil with 0.65mm pin
pitch)
66-Pin TSOP (400 mil with 0.65mm pin
pitch) Lead Free
• Timing - Cycle Time
5ns @ CL = 3
6ns @ CL = 3
• Self Refresh
Standard
Marking
8M816
TG
P
MT46V8M16 – 2 MEGX16X4 BANKS
For the latest data sheet revisions, please refer to the
Micron Website: www.micron.com/dramds
General Description
The DDR SDRAM is a high-speed CMOS, dynamic
random-access memory that operates at a frequency
of 200 MHz (
t
CK=5ns) with a peak data transfer rate of
400Mb/s/p DDR400 continues to use the 2n-prefetch
architecture.
The standard DDR266 data sheet provides a com-
plete description of DDR SDRAM functionality and
operating modes. It provides full specifications and
functionality unless specified herein. This addendum
data sheet concentrates on the critical parameters and
key differences required to support the enhanced DDR
point to point speeds.
Table 1:
Configuration
16 MEG X 8
4 Meg x 8 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
1K (A0-A9)
ARCHITECTURE
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
Table 2:
SPEED
GRADE
Key Timing Parameters
DATA-OUT
WINDOW
2
ACCESS
WINDOW
DQS-DQ
SKEW
CLOCK RATE
CL = 3
1
-5G
-6G
-5G
-6G
none
NOTE:
200 MHz
166 MHz
1.5ns
1.9ns
±0750ps
±0750ps
+500ps
+500ps
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle
09005aef80b2cb48
128Mbx16DDR_PTPadd.fm - Rev. A 4/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
128Mb: x16
GRAPHICAL DDR SDRAM ADDENDUM
Figure 1: 66-pin TSOP Package
Dimension
22.22 ± 0.08
0.71
0.65 TYP
0.32 ± .075 TYP
0.10 (2X)
SEE DETAIL A
Figure 2: 66-pin TSOP Package Pin
Assignment
x8
x16
V
DD
V
DD
DQ0
DQ0
V
DD
Q
V
DD
Q
DQ1
NC
DQ1
DQ2
V
SS
Q
VssQ
DQ3
NC
DQ2
DQ4
V
DD
Q
V
DD
Q
NC
DQ5
DQ3
DQ6
V
SS
Q
VssQ
DQ7
NC
NC
NC
V
DD
Q
V
DD
Q
NC
LDQS
NC
NC
V
DD
V
DD
DNU
DNU
NC
LDM
WE#
WE#
CAS#
CAS#
RAS#
RAS#
CS#
CS#
NC
NC
BA0
BA0
BA1
BA1
A10/AP A10/AP
A0
A0
A1
A1
A2
A2
A3
A3
V
DD
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
11.76 ±0.10
10.16 ±0.08
PIN #1 ID
+0.03
0.15 -0.02
0.10
1.20 MAX
GAGE PLANE
0.25
0.10
+0.10
-0.05
0.80 TYP
0.50 ±0.10
DETAIL A
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
09005aef80b2cb48
128Mbx16DDR_PTPadd.fm - Rev. A 4/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
128Mb: x16
GRAPHICAL DDR SDRAM ADDENDUM
Table 3:
45, 46
Pin Descriptions
SYMBOL
CK, CK#
TYPE
Input
DESCRIPTION
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK
and negative edge of CK#. Output data (DQs and DQS) is referenced to
the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all
banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is
synchronous for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and write
accesses. Input buffers (excluding CK, CK#, and CKE) are disabled
during POWER-DOWN. Input buffers (excluding CKE) are disabled
during SELF REFRESH. CKE is an SSTL_2 input but will detect an
PIN NUMBERS
44
CKE
Input
LVCMOS LOW level after V
DD
is applied and until CKE is first
brought high. After CKE is brought high it becomes an SSTL_2
input
only.
24
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
commandbeingentered.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data during
a WRITE access. DM is sampled on both edges of DQS. Although DM
pins are input-only, the DM loading is designed to match that of DQ
and DQS pins.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.
Data Input/Output.
23, 22,
21
20, 47
RAS#,CAS#,
WE#
DM
Input
Input
26, 27
29-31
32, 35, 36
37, 38, 39
40, 28, 41
BA0, BA1
A0, A1, A2
A3, A4, A5
A6, A7, A8
A9, A10, A11
Input
Input
2, 4, 5, 7, 8, 10, 11,
13, 54, 56, 57, 59,
60, 62, 63, 65
16, 51
DQ0-15
I/O
LDQS/UDQS
I/O
14, 17, 25, 43, 53
19, 50
3, 9, 15, 55, 61
6, 12, 52, 58, 64
1, 18, 33
34, 48, 66
49
NC
DNU
V
DD
Q
V
SS
Q
V
DD
V
SS
V
REF
-
-
Supply
Supply
Supply
Supply
Supply
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data.
No Connect: These pins should be left unconnected.
Do Not Use: Must float to minimize noise on Vref
DQ Power Supply: Isolated on the die for improved noise immunity.
DQ Ground. Isolated on the die for improved noise immunity.
Power Supply.
Ground.
SSTL_2 reference voltage.
09005aef80b2cb48
128Mbx16DDR_PTPadd.fm - Rev. A 4/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
128Mb: x16
GRAPHICAL DDR SDRAM ADDENDUM
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
should be set to 3 clocks, as shown in the CAS Latency
Diagram and Mode Register Definition Diagram.
If a READ command is registered at clock edge
n,
and the latency is
m
clocks, the data will be available
nominally coincident with clock edge
n + m.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Table 4:
SPEED
-5G
-6G
CAS Latency (CL)
ALLOWABLE OPERATING CLOCK FREQUENCY (MHz)
CL = 3
133 MHz
≤
f
≤
200MHz
133 MHz
≤
f
≤
166MHz
CL = 2.5
—
—
CL = 2
—
—
Figure 3: Mode Register Definition
Diagram
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Figure 4: Example CAS Latency
Diagram with CL=3
T0
CK#
14 13
0* 0*
11 10 9 8
Operating Mode
7
6 5 4 3 2 1 0
CAS Latency BT Burst Length
Mode Register (Mx)
T1
T2
T2n
T3
T3n
CK
COMMAND
READ
NOP
NOP
NOP
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CL = 3
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
DQS
DQ
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
TRANSITIONING DATA
DON’T CARE
M3
0
1
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
Reserved
3
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
M11 M10 M9 M8 M7
0
0
-
0
0
-
0
0
-
0
1
-
0
0
-
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
09005aef80b2cb48
128Mbx16DDR_PTPadd.fm - Rev. A 4/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
128Mb: x16
GRAPHICAL DDR SDRAM ADDENDUM
Absolute Maximum Ratings
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
V
DD
Supply Voltage
Relative to Vss ...............................................-1V to +3.6V
V
DD
Q Supply Voltage
Relative to V
SS
..............................................-1V to +3.6V
V
REF
and Inputs Voltage
Relative to V
SS
..............................................-1V to +3.6V
I/O Pins Voltage
Relative to V
SS
................................ -0.5V to V
DD
Q +0.5V
Operating Temperature, T
A
(ambient)....... 0°C to +70°C
Storage Temperature (plastic) ...............-55°C to +150°C
Power Dissipation........................................................ 1W
Short Circuit Output Current .................................50mA
Table 5:
DC Electrical Characteristics and Operating Conditions
SYMBOL
MIN
2.6
2.6
2.5
2.5
0.49 x V
DD
Q
MAX
2.83
2.83
2.7
2.7
0.51 x V
DD
Q
UNITS
V
V
V
V
V
V
V
V
µA
NOTES
36, 41, 53
36, 41,
44,53
36, 41, 53
36, 41,
44,53
6, 44
7, 44
28
28
0°C
≤
T
A
≤
+70°C; Notes: 1–5, 16, Refer to DDR266 Data Sheet, for all notes except 53 below.
PARAMETER/CONDITION
Supply Voltage -5G
I/O Supply Voltage -5G
Supply Voltage -6G
I/O Supply Voltage -6G
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT
Any input 0V
≤
V
IN
≤
V
DD
, V
REF
Pin 0V
≤
VIN
≤
1.35V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V
≤
VOUT
≤
V
DD
Q
)
OUTPUT LEVELS: Full drive option -
V
DD
V
DD
Q
V
DD
V
DD
Q
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
I
I
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-2
V
REF
+ 0.04
V
DD
+ 0.3
V
REF
- 0.15
2
I
OZ
I
OH
I
OL
I
OHR
-5
-16.8
-16.8
-9
5
-
-
-
µA
mA
mA
mA
37, 39
High Current (V
OUT
= V
DD
Q - 0.373V, minimum V
REF
,
minimum V
TT
)
OUTPUT LEVELS: Reduced drive option
38, 39
High Current (V
OUT
= V
DD
Q - 0.763V, minimum V
REF
,
minimum V
TT
)
Low Current (V
OUT
= 0.763V, maximum V
REF
,
maximum V
TT
)
I
OLR
9
-
mA
Note 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at
the DRAM generated from any source other than the DRAM itself may not exceed the DC voltage range.
09005aef80b2cb48
128Mbx16DDR_PTPadd.fm - Rev. A 4/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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