S29WS-J
128/64 Megabit (8/4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memory
Data Sheet
S29WS-J Cover Sheet
Notice to Readers:
This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Notice On Data Sheet Designations
for definitions.
Publication Number
S29WS-J_00
Revision
A
Amendment
6
Issue Date
September 7, 2006
D at a
S hee t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V
IO
range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
ii
S29WS-J
S29WS-J_00_A6 September 7, 2006
S29WS-J
128/64 Megabit (8/4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memory
Data Sheet
Features
Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
Manufactured on 0.11 µm process technology
Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing
erase/program functions in other bank
– Zero latency between read and write operations
– Four bank architecture: WS128J: 16Mb/48Mb/48Mb/16Mb,
WS064J: 8Mb/24Mb/24Mb/8Mb
– Simultaneous Operation: 60 mA @ 80Mhz
– Program/Erase: 15 mA
– Standby mode: 0.2 µA
Handshaking feature available
– Provides host system with minimum possible latency by monitoring
RDY
Hardware reset input (RESET#)
– Hardware method to reset the device for reading array data
Programable Burst Interface
– 2 Modes of Burst Read Operation
– Linear Burst: 8, 16, and 32 words with wrap-around
– Continuous Sequential Burst
WP# input
– Write protect (WP#) function allows protection of four outermost
boot sectors, regardless of sector protect status
Persistent Sector Protection
– A command sector protection method to lock combinations of
individual sectors and sector groups to prevent program or erase
operations within that sector
– Sectors can be locked and unlocked in-system at V
CC
level
Secured Silicon Sector region
– 128 words accessible through a command sequence, 64words for
the Factory Secured Silicon Sector and 64words for the Customer
Secured Silicon Sector.
Sector Architecture
4 Kword x 16 boot sectors, eight at the top of the address
range, and eight at the bottom of the address range
–
WS128J:
4 Kword X 16, 32 Kword x 254 sectors
Bank A : 4 Kword x 8, 32 Kword x 31 sectors
Bank B : 32 Kword x 96 sectors
Bank C : 32 Kword x 96 sectors
Bank D : 4 Kword x 8, 32 Kword x 31 sectors
–
WS064J:
4 Kword x 16, 32 Kword x 126 sectors.
Bank A : 4 Kword x 8, 32 Kword x 15 sectors
Bank B : 32 Kword x 48 sectors
Bank C : 32 Kword x 48 sectors
Bank D : 4 Kword x 8, 32 Kword x 15 sectors
Password Sector Protection
– A sophisticated sector protection method to lock combinations of
individual sectors and sector groups to prevent program or erase
operations within that sector using a user-defined 64-bit password
ACC input: Acceleration function reduces programming
time; all sectors locked when ACC = V
IL
CMOS compatible inputs, CMOS compatible outputs
Low V
CC
write inhibit
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
– Backwards compatible with Am29BDS, Am29BDD, Am29BL, and
MBM29BS families
WS128J : 84-ball (8 mm x 11.6 mm) FBGA package,
WS064J : 80-ball (7 mm x 9 mm) FBGA package
Cyclling Endurance : 1,000,000 cycles per sector typical
Data retention : 20-years typical
Read access times at 80/66 MHz
– Synchronous latency of 71/56 ns (at 30 pF)
– Asynchronous random access times of 55/55 ns (at 30 pF)
Data# Polling and toggle bits
– Provides a software method of detecting program and erase
operation completion
Erase Suspend/Resume
– Suspends an erase operation to read data from, or program data to,
a sector that is not being erased, then resumes the erase operation
Power dissipation (typical values, C
L
= 30 pF)
– Burst Mode Read: 18 mA @ 80Mhz
Unlock Bypass Program command
– Reduces overall programming time when issuing multiple program
command sequences
General Description
The S29WS-J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device,
organized as 8,388,608/4,194,304 words of 16 bits each. This device uses a single V
CC
of 1.65 to 1.95 V to read, program, and
erase the memory array. A 12.0-volt V
HH
on ACC may be used for faster program performance if desired. The device can also
be programmed in standard EPROM programmers.
Publication Number
S29WS-J_00
Revision
A
Amendment
6
Issue Date
September 7, 2006
D at a
S hee t
At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns at 30 pF. At 66 MHz,
the device provides a burst access of 11.2 ns at 30 pF with a latency of 56 ns at 30 pF. The device operates
within the wireless temperature range of -25°C to +85°C, and is offered in Various FBGA packages.
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space
into four banks. The device can improve overall system performance by allowing a host system to program or
erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This
releases the system from waiting for the completion of program or erase operations.
The device is divided as shown in the following table:
Quantity
Bank
A
31
B
C
D
8
8
4 Kwords
96
96
31
15
48
48
15
32 Kwords
32 Kwords
32 Kwords
32 Kwords
128Mb
8
64 Mb
8
Size
4 Kwords
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to
control asynchronous read and write operations. For burst operations, the device additionally requires Ready
(RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of
microprocessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to the device. The user can
preset the burst length and wrap through the same memory space, or read the flash array in continuous
mode.
The clock polarity feature provides system designers a choice of active clock edges, either rising or falling.
The active clock edge initiates burst accesses and determines when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Commands are written to the command register using standard microprocessor write timing. Register
contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading
data out of the device is similar to reading from other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the user to put erase or program on hold for any period
of time to read data from, or program data to, any sector that is not selected for erasure. True background
erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program
area) after an erase suspend, then the user must use the proper command sequence to enter and exit this
region. Program suspend is also offered.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory
device.
The host system can detect whether a program or erase operation is complete by using the device status bit
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The device also offers two types of data protection at the sector level. When at V
IL
,
WP#
locks the four outermost boot sectors.
The device offers two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both modes.
2
S29WS-J
S29WS-J_00_A6 September 7, 2006
Data
She et
Spansion™ Flash memory products combine years of Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
September 7, 2006 S29WS-J_00_A6
S29WS-J
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