DS28E04-100
4096-Bit Addressable 1-Wire EEPROM
with PIO
www.maxim-ic.com
GENERAL DESCRIPTION
The DS28E04-100 is a 4096-bit, 1-Wire EEPROM
chip with seven address inputs. The address inputs
are directly mapped into the 1-Wire 64-bit Device ID
Number to easily enable the host system to identify
the physical location or functional association of the
DS28E04-100 in a multidevice 1-Wire network en-
vironment. The 4096-bit EEPROM array is configured
as 16 pages of 32 bytes with a 32 byte scratchpad to
perform write operations. EEPROM memory pages
can be individually write protected or put in EPROM-
emulation mode, where bits can only be changed
from a 1 to a 0 state. In addition to the memory, the
DS28E04-100 has two general-purpose I/O ports that
can be used for input or to generate level and/or
pulse outputs. Activity registers also capture port
activity for state change monitoring. The DS28E04-
100 communicates over the single-contact 1-Wire
bus. The communication follows the standard Dallas
Semiconductor 1-Wire protocol.
®
FEATURES
·
·
·
4096 bits of EEPROM Memory Partitioned into
16 Pages of 256 Bits
Seven Address Inputs for Physical Location
Configuration
Two General-Purpose PIO Pins with Pulse-
Generation Capability
Individual Memory Pages can be Permanently
Write-Protected or put in OTP EPROM-
Emulation Mode (“Write to 0”)
Communicates to Host with a Single Digital
Signal at 15.3kbps or 111kbps Using 1-Wire
Protocol
Parasitic or V
CC
Powered
Conditional Search Based on PIO Status or PIO
Activity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Reads and Writes Over a Wide 2.8V to 5.25V
Voltage Range from -40°C to +85°C
16-Pin, 150-mil SO Package
§
§
§
§
§
§
§
APPLICATIONS
·
Autoconfiguration of Modular Systems such as
Central-Office Switches, Cellular Base Stations,
Access Products, Optical Network Units, and
PBXs
Accessory/PCB Identification
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS28E04S-100
-40°C to +85°C 16 SO (150 mils)
DS28E04S-100/T&R -40°C to +85°C Tape-and-Reel
·
TYPICAL OPERATING CIRCUIT
V
CC
R
PUP
PIN CONFIGURATION
A3
A2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IO
A4
A5
A6
GND
N.C.
P1
P0
PX.Y
µC
LED
IO V
CC
POL
P1
P0
GND
DS28E04 #1
A6
IO V
CC
POL
P1
P0
A6
A1
A0
GND
A0
RST1 RST0
GND
DS28E04 #7
A0
N.C.
V
CC
POL
SO (150 mils)
Commands, Registers, and Modes are capitalized for
clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 102704
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
ABSOLUTE MAXIMUM RATINGS
All Pins: Voltage to GND
All Pins: Sink Current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Soldering Temperature
-0.5V, +6V
20mA
-40°C to +85°C
+150°C
-40°C to +85°C
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
PUP
= 2.8V to 5.25V, V
CC
= V
PUP
, floated or grounded, T
A
= -40°C to +85°C.)
PARAMETER
Ground Current
Supply Current
Standby Supply Current
PINS A0 TO A6
Input Low Voltage
Input High Voltage
Input Load Current
POL PIN
Input Low Voltage
Input High Voltage
Leakage Current
PIO PINS
Input Low Voltage
Input High Voltage
Output Low Voltage at
4mA
Leakage Current
Minimum Sensed PIO
Pulse
Output Pulse Duration
IO PIN GENERAL DATA
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Input High Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
(Notes 1, 15)
Rising-Edge Hold-Off Time
(Note 3)
Time Slot Duration
(Note 1)
SYMBOL
I
GND
CONDITIONS
(Notes 1, 2, 3)
V
CC
= V
PUP
(Note 3)
Device idle; A0 to A6 floating
(Note 1)
V
X
= max(V
PUP
, V
CC
) (Note 1)
Pin at GND (Note 4)
(Note 1)
V
X
= max(V
PUP
, V
CC
) (Note 1)
Pin at 5.25V
(Note 1)
V
X
= max(V
PUP
, V
CC
) (Note 1)
(Note 5)
Pin at 5.25V
(Note 6)
(Note 7)
(Notes 1, 8)
(Notes 3, 9)
IO pin at V
PUP
, A0 to A6 floating, V
CC
at
GND
IO pin at V
PUP
, A0 to A6 floating, V
CC
at
V
PUP
(Notes 3, 10, 11)
(Notes 1, 12)
V
X
= max(V
PUP
, V
CC
) (Note 1)
(Notes 3, 10, 13)
(Notes 3, 10, 14)
At 4mA Current Load (Note 5)
Standard speed, R
PUP
= 2.2kW
Overdrive speed, R
PUP
= 2.2kW
Overdrive speed, directly prior to reset
pulse; R
PUP
= 2.2kW
Standard speed (Note 16)
Overdrive speed
Standard speed
Overdrive speed
V
X
-
0.3V
1.0
0.21
5
2
5
0.5
Not applicable (0)
65
9
5.0
µs
µs
4.9
1.70
0.4
1
250
0.3
100
0.05
0.05
0.46
V
X
-
0.3V
0.4
1
10
1000
2.2
800
11.00
µA
8.25
4.40
0.3
V
V
V
V
V
V
µs
V
X
-
0.3V
1
0.30
V
X
-
0.3V
-1.1
0.30
MIN
TYP
MAX
20
1
11
0.30
UNITS
mA
mA
µA
V
V
µA
V
V
µA
V
V
V
µA
µs
ms
kW
pF
I
CC
I
CCS
V
ILA
V
IHA
I
LA
V
ILPOL
V
IHPOL
I
LKPOL
V
ILP
V
IHP
V
OLP
I
LKP
t
PWMIN
t
PULSE
R
PUP
C
IO
I
L
V
TL
V
IL
V
IH
V
TH
V
HY
V
OL
t
REC
t
REH
t
SLOT
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PARAMETER
SYMBOL
CONDITIONS
IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed, V
PUP
> 4.5V
Standard speed (Note 17)
Reset Low Time (Note 1)
t
RSTL
Overdrive speed, V
PUP
> 4.5V
Overdrive speed (Note 17)
Presence-Detect High
Standard speed
t
PDH
Time
Overdrive speed (Note 17)
Standard speed, V
PUP
> 4.5V
Presence-Detect Fall Time
t
FPD
Standard speed
(Notes 3, 18)
Overdrive speed
Standard speed
Presence-Detect Low
t
PDL
Overdrive speed, V
PUP
> 4.5V
Time
Overdrive speed (Note 17)
Standard speed, V
PUP
> 4.5V
Presence-Detect Sample
t
MSP
Standard speed
Time (Note 1)
Overdrive speed
IO PIN, 1-Wire WRITE
Standard speed
Write-0 Low Time (Note 1)
t
W0L
Overdrive speed (Note 17)
Standard speed
Write-1 Low Time
t
W1L
(Notes 1, 19)
Overdrive speed
IO PIN, 1-Wire READ
Standard speed
Read Low Time
t
RL
(Notes 1, 20)
Overdrive speed
Standard speed
Read Sample Time
t
MSR
(Notes 1, 20)
Overdrive speed
EEPROM
Programming Current
I
PROG
(Note 21)
Programming Time
t
PROG
(Note 22)
Write/Erase Cycles
At +25°C
N
CY
(Endurance)
At +85°C (worst case)
Data Retention
t
DR
At +85°C (worst case)
MIN
480
504
48
53
15
2
1.10
1.1
0
60
8
8
64
67
8.1
60
7
5
1
5
1
t
RL
+
d
t
RL
+
d
TYP
MAX
640
640
80
80
60
7
3.75
7.0
1.1
240
24
26
75
75
10
120
16
15 -
e
2-
e
15 -
d
2-
d
15
2
1
10
200k
50k
10
UNITS
µs
µs
µs
µs
µs
µs
µs
µs
µs
mA
ms
¾
years
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
System requirement.
Maximum instantaneous pulldown current through all pins combined.
Guaranteed by design, simulation only. Not production tested.
This load current is caused by the internal weak pullup, which asserts a logical 1 to address pins that are not connected. The
logical state of the address pins must not change during the execution of ROM function commands during those time slots in
which these bits are relevant.
The I-V characteristic is linear for voltages less than 1V.
Width of the narrowest pulse that trips the activity latch. Back to back pulses that are active for < t
PWMIN
(max) and that have an
intermediate inactive time < t
PWMIN
(max) are not guaranteed to be filtered.
The Pulse function requires that V
CC
power is available; otherwise the command will not be executed.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Capacitance on the data pin could be 800pF when V
PUP
is first applied. If a 2.2kW resistor is used to pull up the data line, 2.5µs
after V
PUP
has been applied the parasite capacitance will not affect normal communications.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO needs to be less than or equal to V
ILMAX
whenever the master drives the line low.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO has to drop by at least V
HY
to be detected as logic '0'.
Applies to a single DS28E04-100 without V
CC
supply, attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been previously reached.
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table.
Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
e
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
.
d
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high threshold of the bus
master.
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Note 21:
Note 22:
Current drawn during the EEPROM programming interval. If the device does not get V
CC
power, the pullup circuit on IO during the
programming interval should be such that the voltage at IO is greater than or equal to V
PUP
(min). If V
PUP
in the system is close to
Vpup(min) then a low-impedance bypass of R
PUP
that can be activated during programming may need to be added.
The t
PROG
interval begins t
REHmax
after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
or I
CCS
, respectively.
PARAMETER
t
SLOT
(incl. t
REC
)
t
RSTL
t
PDH
t
PDL
t
W0L
1)
LEGACY VALUES
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
61µs
(undef)
7µs
(undef)
480µs
(undef)
48µs
80µs
15µs
60µs
2µs
6µs
60µs
240µs
8µs
24µs
60µs
120µs
6µs
16µs
DS28E04-100 VALUES
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
1)
65µs
(undef)
9µs
(undef)
504µs
640µs
53µs
80µs
15µs
60µs
2µs
7µs
60µs
240µs
8µs
26µs
60µs
120µs
7µs
16µs
Intentional change, longer recovery time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
PIN
1
2
3
4
5, 12
6, 11
7
8
9
10
13
14
15
16
NAME
A3
A2
A1
A0
GND
N.C.
V
CC
POL
P0
P1
A6
A5
A4
IO
FUNCTION
Address bit input (place value = 8), with weak pullup.
Address bit input (place value = 4), with weak pullup.
Address bit input (place value = 2), with weak pullup.
Least significant address bit input (place value = 1), with weak pullup.
Ground Reference
Not Connected
Optional power supply for the chip; float or ground if V
CC
power is not available.
Power-up polarity (logical state) for P0 and P1; pin has a weak pulldown.
Remote-controlled I/O pin, open drain with weak pulldown.
Remote-controlled I/O pin, open drain with weak pulldown.
Address bit input (place value = 64), with weak pullup.
Address bit input (place value = 32), with weak pullup.
Address bit input (place value = 16), with weak pullup.
1-Wire Bus Interface. Open drain, requires external pullup resistor.
DETAILED DESCRIPTION
The DS28E04-100 combines 4096 bits of EEPROM, a 16-byte control page, two general-purpose PIO pins, seven
external address pins, and a fully featured 1-Wire interface in a single chip. PIO outputs are configured as open-
drain and provide an on-resistance of 100W max. A robust PIO channel-access communication protocol ensures
that PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the
scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the
scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory
location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this
number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number
guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus and operate independently of each other. The DS28E04-
100 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity. The
DS28E04-100 has an optional V
CC
supply connection. When an external supply is absent, device power is supplied
parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of
the 1-Wire bus power source. Applications of the DS28E04-100 include autoconfiguration and state monitoring of
modular systems such as central-office switches, cellular base stations, access products, optical network units, and
PBXs, and accessory/PC board identification.
4 of 36
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte
scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the eight
ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip
ROM, 6) Resume, 7) Overdrive-Skip ROM or 8) Overdrive-Match ROM. Upon completion of an Overdrive ROM
command byte executed at standard speed, the device enters Overdrive mode where all subsequent
communication occurs at a higher speed. The protocol required for these ROM function commands is described in
Figure 14. After a ROM function command is successfully executed, the memory/control functions become
accessible and the master may provide any one of the nine Memory/Control Function commands. The protocol for
these commands is described in Figure 9.
All data is read and written least significant bit first.
Figure 1. Block Diagram
Internal V
DD
V
CC
1-Wire Network
IO
1-Wire
Function Control
Device ID
Number Register
A0
Memory
Function
Control Unit
P0
P1
POL
PIO
Control Registers
A6
CRC16
Generator
Data Memory
16 Pages of
32 Bytes Each
Special Function
Registers
32-Byte
Scratchpad
Internal V
DD
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