DDR SDRAM 512Mb D-die (x8)
Preliminary
DDR SDRAM
512Mb D-die DDR SDRAM Specification
54 sTSOP-II with Pb-Free (400mil x 441mil)
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 June. 2005
DDR SDRAM 512Mb D-die (x8)
Table of Contents
Preliminary
DDR SDRAM
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ...................................................................................................................4
3.0 Operating Frequencies................................................................................................................4
4.0 Pin Description ............................................................................................................................5
5.0 Package Physical Dimension .....................................................................................................6
6.0 Block Diagram (16Mbit x8 I/O x4 Banks) ...................................................................................7
7.0 Input/Output Function Description ............................................................................................8
8.0 Command Truth Table.................................................................................................................9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
15.0 DDR SDRAM IDD spec table ..................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot specification for Address and Control Pins............................14
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ..............................................................................17
21.0 Component Notes ....................................................................................................................18
22.0 System Notes ...........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 0.1 June. 2005
DDR SDRAM 512Mb D-die (x8)
Revision History
Revision
0.0
0.1
Month
April
June
Year
2005
2005
- First version for internal review
- Changed Mater format
History
Preliminary
DDR SDRAM
Rev. 0.1 June. 2005
DDR SDRAM 512Mb D-die (x8)
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 54pin sTSOP(II)-400
Pb-Free
package
•
RoHS compliant
Preliminary
DDR SDRAM
2.0 Ordering Information
Part No.
K4H510838D-VC/LCC
K4H510838D-VC/LB3
K4H510838D-VC/LA2
K4H510838D-VC/LB0
64M x 8
Org.
Max Freq.
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
54pin sTSOP II
Interface
Package
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 0.1 June. 2005
DDR SDRAM 512Mb D-die (x8)
4.0 Pin Description
Preliminary
DDR SDRAM
64Mb x 8
VDD
DQ0
VDDQ
DQ1
VSSQ
DQ2
VDDQ
DQ3
VSSQ
NC
VDDQ
NC
NC
VDD
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
VSSQ
DQS
VREF
VSS
DM
CK
CK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
54 Pin sTSOP(II)
400mil x 441mil
(0.4 mm Pin Pitch)
Bank Address
BA0-BA1
Row Address
A0-A12
Auto Precharge
A10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
512Mb sTSOP(II)-400 Package Pinout
Organization
64Mx8
Row Address
A0~A12
Column Address
A0-A9, A11
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 0.1 June. 2005
嵌入式系统
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