IDTCV105B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
IDTCV105B
PRELIMINARY
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION:
4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
IDTCV105B is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrum selection.
KEY SPECIFICATION:
•
•
•
•
CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
EasyN
Programming
CPU CLK
Output Buffers
CPU[1:0]
CPU_ITP
X1
XTAL
Osc Amp
I
REF
REF 1.0
X2
PLL2
SSC
EasyN
Programming
SDATA
SCLK
SM Bus
Controller
3V66/PCI
Output Buffers
PCI[5:0], PCIF[2:0]
3V66[3:0]
PLL3
SSC
V
TT_PWRGD
Watch Dog
Timer
FS[1:0]
Control
Logic
SRC CLK
Output Buffer
SRC
I
REF
48MHz[1:0]
S
EL
24_48#
PLL4
48MHz
Output Buffer
RESET#
OUTPUT TABLE
CPU (Pair)
3
3V66
3
3V66/VCH
1
PCI
6
PCIF
3
REF
2
48MHz
2
24 - 48MHz
0
SRC (Pair)
1
Reset#
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2003 Integrated Device Technology, Inc.
SEPTEMBER 2003
DSC-6392/7
IDTCV105B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
*FS1/REF0
*FS0/REF1
V
DD
_REF
X1
X2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min
Max
4.6
4.6
+150
+70
+115
Unit
V
V
°C
°C
°C
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DDA
V
SS
IREF
CPUT_ITP
CPUC_ITP
V
SS
CPUT1
CPUC1
V
DD_
CPU
CPUT0
CPUC0
V
SS
SRCT
SRCC
V
DDA
V
DDIN
T
STG
T
AMBIENT
T
CASE
ESD Prot
–65
0
2000
V
SS
PCIF0
PCIF1
PCIF2
V
DD_
PCI
V
SS
PCI0
PCI1
PCI2
PCI3
V
DD_
SRC
*V
TT
_P
WRGD#
*SDATA
*SCLK
V
DD_
PCI
V
SS
PCI4
PCI5
*RESET#/PD#
48MHz1
48MHz0
HW FREQUENCY SELECTION
FS1.0
00
01
10
11
CPU
100
200
133.33
166.67
AGP
66.66
66.66
66.66
66.66
PCI
33.3
33.3
33.3
33.3
N Resolution
0.223721591
0.447443181
0.298295454
0.397727272
3V66_0
3V66_1
V
SS
V
DD_
3V66
3V66_2
3V66_3/VCH
V
SS
V
DD
48
* = ~ 130KΩ internal pull-up.
** = ~ 130KΩ internal pull-down.
SSOP
TOP VIEW
2
IDTCV105B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
SW FREQUENCY SELECTION
WDBS[2:0] or
BS[2:0] = 000
100
100.9
102.91
104.93
110.07
114.99
119.91
125.06
0.223721591
447
WDBS[2:0] or
BS[2:0] = 001
200.01
201.8
204.93
209.85
215.22
220.14
225.06
229.99
0.447443181
447
BS[2:0] and WBS[2:0] are band selects. Whenever there is a band switch, the user has to issue a WD soft alarm (see Byte 32 and Byte 33).
In CPU N/M programming, CPU frequency = N * resolution, N from 290 - 600.
CFS[3:0]
000
001
010
011
100
101
110
111
N Resolution
Corresponding N
WDBS[2:0] or
BS = 010
133.34
135.13
138.11
139.9
141.99
144.97
147.95
150.05
0.298295454
447
WDBS[2:0] or
BS[2:0] = 011
166.65
167.84
169.83
173.01
175
178.18
180.17
184.94
0.397727272
419
0.447443181
447
0.894886363
447
0.894886363
298
0.795454544
419
WDBS[2:0] or
BS[2:0] = 100
200.01
66.67
WDBS[2:0] or
BS[2:0] = 101
400.01
401.8
WDBS[2:0] or
BS[2:0] = 110
266.66
267.57
WDBS[2:0] or
BS[2:0] = 111
333.3
334.89
SPREAD SPECTRUM MAGNITUDE
CONTROL (SMC)
SMC[2:0]
000
001
010
011
100
101
110
111
Off
- 0.25
- 0.5
- 0.75
-1
± 0.125
± 0.25
± 0.375
3V66-PCI/F SKEW
Skew[2:0]
000
001
010
011
100
101
110
111
normal, 3V66 leads PCI 2.5ns
move forward 200ps
move forward 400ps
move forward 600ps
move backward 200ps
move backward 400ps
move backward 600ps
move backward 800ps
AGP/PCI FREQUENCY SELECTION
AFS[2:0]
000
001
010
011
100
101
110
111
AGP
66.67
68.68
70.7
72.71
74.5
76.51
78.53
80.54
PCI
33.33
34.34
35.35
36.35
37.25
38.26
39.26
40.27
Corresponding N
298
307
316
325
333
342
351
360
AGP/PCI STRENGTH
Str[1:0]
0, 0
0, 1
1, 0
1, 1
1.2x
0.7x
0.8x
1x
In AGP/PCI N/M programming, AGP frequency = N * 0.223721591, N from
290 - 600
REF STRENGTH
REF Str[1:0]
0, 0
0, 1
1, 0
1, 1
1x
0.8x
1.2x
0.7x
3
IDTCV105B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
FS1/REF0
FS0/REF1
V
DD
_REF
X1
X2
V
SS
PCIF0
PCIF1
PCIF2
V
DD
_PCI
V
SS
PCI0
PCI1
PCI2
PCI3
V
DD
_PCI
V
SS
PCI4
PCI5
RESET#/PD#
48MHz1
48MHz0
V
SS
V
DD
48
3V66_3/VCH
3V66_2
V
DD
_3V66
V
SS
3V66_1
3V66_0
SCLK
SDATA
V
TT
_P
WRGD
#
V
DD
_SRC
SRCC
SRCT
V
SS
CPUC0
CPUT0
V
DD
_CPU
Type
I/O
I/O
PWR
IN
OUT
GND
I/O
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
PWR
GND
OUT
OUT
IN
I/O
IN
PWR
OUT
OUT
GND
OUT
OUT
PWR
Description
Frequency select latch input 3.3V input HIGH/LOW voltage/ 14.318MHz reference clock output
(1)
Frequency select latch input 2.5V input HIGH/LOW voltage/ 14.318MHz reference clock output
(1)
3.3V
Xtal input
Xtal output
GND
Frequency select latch input 3.3V input HIGH/LOW voltage/ PCI free running clock
(2)
PCI free running clock
PCI free running clock
3.3V
GND
PCI clock
PCI clock
PCI clock
PCI clock
3.3V
GND
PCI clock
PCI clock
Reset output signal from watchdog circuit, active LOW/ power down control input. Mode selectable through
SM bus, power on is RESET# mode.
(1)
48MHz clock output
48MHz clock output. Phase is 180 different with 24_48, 48MHz1, and VCH. Output drive stength can
be doubled through SM programming.
GND
3.3V
66MHz or 48MHz clock output. Selectable by SM bus. Power on is 66MHz.
66MHz clock output
3.3V
GND
66MHz clock output
66MHz clock output
SM bus clock
(1)
SM bus data
(1)
Used for power on latch, active LOW
(1)
3.3V
SATA 0.7V current mode differential clock output
SATA 0.7V current mode differential clock output
GND
Hosts 0.7V current mode differential clock output
Hosts 0.7V current mode differential clock output
3.3V
NOTES:
1. ~ 130KΩ internal pull-up.
2. ~ 130KΩ internal pull-down.
4
IDTCV105B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
41
42
43
44
45
46
47
48
Name
CPUC1
CPUT1
V
SS
CPUC_ITP
CPUT_ITP
IREF
V
SS
V
DDA
Type
OUT
OUT
GND
OUT
OUT
OUT
GND
PWR
Hosts 0.7V current mode differential clock output
Hosts 0.7V current mode differential clock output
GND
Hosts 0.7V current mode differential clock output
Hosts 0.7V current mode differential clock output
Reference current for differential output
GND
3.3V
Description
5
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