FemtoClock
®
NG Crystal-to-HCSL
Frequency Synthesizer
841N4830
Datasheet
General Description
The 841N4830 is a 3 HCSL, 1 LVPECL and 2 LVCMOS output
Synthesizer optimized to generate PCI Express reference clock
frequencies. The device uses IDT’s fourth generation FemtoClock
®
NG technology for synthesis of high clock frequency at very low
phase noise. It provides low power consumption with good power
supply noise rejection. Using a 25MHz, 12pF parallel resonant
crystal, the following frequencies can be generated: 100MHz,
50MHz and 25MHz. Maximum rms phase jitter of 0.36ps, easily
meets PCI Express jitter requirements. The 841N4830 is packaged
in a small 32-pin VFQFN package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
Next Generation (NG) technology
Three differential HCSL outputs, one differential LVPECL and
two single-ended LVCMOS/LVTTL outputs
Crystal oscillator interface designed for a 25MHz, 12pF parallel
resonant crystal
CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
A 25MHz crystal generates output frequencies of: 100MHz,
50MHz and 25MHz
VCO frequency: 2GHz
RMS Phase Jitter @ 100MHz, (12kHz – 20MHz) using a 25MHz
crystal: 0.36ps (maximum)
Power supply noise rejection PSNR: -45dB (typical)
PCI Express Gen 2 (5 Gb/s) jitter compliant
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nOE_REF
Pulldown
25MHz LVPECL
Pin Assignment
nOEA
IREF
nQA0
REF_OUT
PLL_BYPASS
Pulldown
nOEA
Pulldown
25MHz
nREF_OUT
32 31 30 29 28 27 26 25
PLL_BYPASS
nOE_REF
nOEB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
24
QA1
nQA1
V
DDO
QA2
nQA2
GND
QA3
V
DDO_QA3
841N4830
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
GND
23
22
21
20
19
18
17
V
DDO
V
DDA
XTAL_IN
1
100MHz HCSL
OSC
XTAL_OUT
CLK
Pulldown
nCLK
Pullup
CLK_SEL
Pullup
0
PFD
&
LPF
1
FemtoClock® NG
VCO
2GHz
3
QA[2:0]
÷20
0
3
nQA[2:0]
100MHz LVCMOS
DIV2_QB
V
DDA
CLK
nCLK
V
DDO_REF
QA3
V
DD_OSC
nREF_OUT
REF_OUT
CLK_SEL
XTAL_IN
0
100/50MHz
LVCMOS
IREF
QB
÷80
÷2
1
DIV2_QB
Pullup
nOEB
Pulldown
©2016 Integrated Device Technology, Inc.
1
Revision F, May 23, 2016
XTAL_OUT
V
DDO_QB
QB
÷1
QA0
V
DD
841N4830 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5, 32
6
7
8
9, 10
11
12
13
14
15
16
17
18
19, 25
20, 21
22, 29
23, 24
26, 27
28
Name
PLL_BYPASS
nOE_REF
nOEB
DIV2_QB
V
DDA
CLK
nCLK
V
DDO_REF
REF_OUT,
nREF_OUT
CLK_SEL
XTAL_IN
XTAL_OUT
V
DD_OSC
V
DDO_QB
QB
V
DDO_QA3
QA3
GND
nQA2, QA2
V
DDO
nQA1, QA1
nQA0, QA0
IREF
Input
Input
Input
Input
Power
Input
Input
Power
Output
Input
Input
Power
Power
Output
Power
Output
Power
Output
Power
Output
Output
Pullup
Type
Pulldown
Pulldown
Pulldown
Pullup
Description
When HIGH, PLL is bypassed and outputs are driven by input crystal or clock. When
LOW outputs are driven by PLL. LVCMOS/LVTTL interface levels. See Table 3D.
Output enable signal for REF_OUT output. When LOW, outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3C.
Output enable signal for Bank B. When LOW, QB output is enabled. When HIGH,
selects high impedance mode. LVCMOS/LVTTL interface levels.See Table 3B.
Select signal for the output divider for Bank B. LVCMOS/LVTTL clock output. See
Table 3F.
Analog supply pins.
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Output power supply pin for LVPECL reference outputs.
25MHz differential reference output pair. LVPECL interface levels.
Input select signal. When HIGH, selects CLK, nCLK inputs. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.See Table 3E.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
Core supply pin for crystal oscillator.
Output power supply pin for Bank B LVCMOS output.
Single-ended output. LVCMOS/LVTTL interface levels.
Output power supply pin for QA3 LVCMOS output.
Single-ended output. LVCMOS/LVTTL interface levels.
Power supply ground.
100MHz differential output pair. HCSL interface levels.
Output power supply pins for Bank A HCSL outputs.
100MHz differential output pair. HCSL interface levels.
100MHz differential output pair. HCSL interface levels.
0.7V current reference resistor output. An external fixed precision resistor (475) from
this pin to ground provides a reference current used for differential current-mode QAx,
nQAx clock outputs.
Input
Power
Pulldown
Output Enable signal for Bank A. When LOW enables output. When HIGH selects
high impedance mode. LVCMOS/LVTTL interface levels.See Table 3A.
Core supply pin.
30
31
nOEA
V
DD
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc.
2
Revision F, May 23, 2016
841N4830 Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Control Pins
Input Pullup Resistors
Input Pulldown Resistors
Power Dissipation
Capacitance (per output)
Output
Impedance
QA3, QB
V
DD,
V
DD_OSC,
V
DDO,
V
DDO_REF,
V
DDO_QA3,
V
DDO_QB
= 3.6V
V
DDO_QA3,
V
DDO_QB
= 3.6V
4
100
100
5
25
pF
k
k
pF
Test Conditions
CLK, nCLK
Minimum
Typical
2
Maximum
Units
pF
Function Tables
Table 3A. nOEA Function Table
Input
nOEA
0 (default)
1
Outputs
QA
Active
High-Impedance
Table 3B. nOEB Function Table
Input
nOEB
0 (default)
1
Outputs
QB
Active
High-Impedance
Table 3C. nOE_REF Function Table
Input
nOE_REF
0 (default)
1
Outputs
REF_OUT
Active
High-Impedance
Table 3D. PLL_BYPASS Function Table
Input
PLL_BYPASS
0 (default)
1
Outputs
QA, QB
PLL
Bypass PLL
Table 3E. CLK_SEL Function Table
Input
CLK_SEL
0
1 (default)
Selected Input
XTAL
CLK, nCLK
Table 3F. DIV2_QB Function Table
Input
DIV2_QB
0
1 (default)
Output Frequency
100MHz
50MHz
©2016 Integrated Device Technology, Inc.
3
Revision F, May 23, 2016
841N4830 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
(LVCMOS, HCSL)
Outputs, I
O
(LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
50mA
100mA
37.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DD_OSC
= 3.0V to 3.6V, V
DDO
= V
DDO_QA3
= V
DDO_QB
= V
DDO_REF
=
2.7V to 3.6V, T
A
= -40°C to 85°C
Symbol
V
DD,
V
DD_OSC
V
DDA
V
DDO,
V
DDOx
I
EE
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Included in I
EE
Test Conditions
Minimum
3.0
V
DD
– 0.32
2.7
Typical
3.3
3.3
3.3
Maximum
3.6
V
DD
3.6
170
32
Units
V
V
V
mA
mA
V
DDOx
denotes V
DDO_REF,
V
DDO_QA3
and V
DDO_QB
.
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.0V to 3.6V, V
DDO_QA3
= V
DDO_QB
= 2.7V to 3.6V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
CLK_SEL,
DIV2_QB
I
IH
Input
High Current
nOEA, nOEB,
nOE_REF,
PLL_BYPASS
CLK_SEL,
DIV2_QB
I
IL
Input
Low Current
nOEA, nOEB,
nOE_REF,
PLL_BYPASS
V
DD
= V
IN
= 3.6V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
V
DD
= V
IN
= 3.6V
150
µA
V
DD
= 3.6V, V
IN
= 0V
-150
µA
V
DD
= 3.6V, V
IN
= 0V
-5
µA
©2016 Integrated Device Technology, Inc.
4
Revision F, May 23, 2016
841N4830 Datasheet
Table 4C. Differential DC Characteristics,
V
DD
= 3.0V to 3.6V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High
Current
Input Low
Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.6V
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVPECL DC Characteristics,
V
DDO_REF
= 2.7V to 3.6V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
DDO_REF
– 1.4
V
DDO_REF
– 2.0
0.6
Typical
Maximum
V
DDO _REF
– 0.9
V
DDO_REF
– 1.7
1.0
Units
V
V
V
NOTE 1: Output termination with 50 to V
DDO_REF
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
pF
Maximum
Units
©2016 Integrated Device Technology, Inc.
5
Revision F, May 23, 2016
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
