CY7C1318JV18
CY7C1320JV18
18 Mbit DDR II SRAM Two Word Burst
Architecture
Features
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Functional Description
The CY7C1318JV18, and CY7C1320JV18 are 1.8V
Synchronous Pipelined SRAMs equipped with DDR II archi-
tecture. The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a one bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. For CY7C1318JV18 and CY7C1320JV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18 bit words (in the case of
CY7C1318JV18) of two 36 bit words (in the case of
CY7C1320JV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self timed write circuitry.
18 Mbit Density (1M x 18, 512K x 36)
300 MHz Clock for High Bandwidth
Two word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 600 MHz) at 300 MHz
Two Input Clocks (K and K) for Precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to Minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
systems
Synchronous Internally self timed Writes
DDR II Operates with 1.5 Cycle Read Latency when the DLL
is enabled
Operates similar to a DDR I Device with 1 Cycle Read Latency
in DLL Off Mode
1.8V Core Power Supply with HSTL Inputs and Outputs
Variable drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4V–V
DD
)
Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 Compatible Test Access Port
Delay Lock Loop (DLL) for Accurate Data Placement
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Configurations
CY7C1318JV18 – 1M x 18
CY7C1320JV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
300 MHz
300
655
730
250 MHz
250
600
635
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-15271 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 25, 2009
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CY7C1318JV18
CY7C1320JV18
Logic Block Diagram (CY7C1318JV18)
A0
Burst
Logic
A
(19:0)
20
LD
K
K
19
Write Add. Decode
Read Add. Decode
A
(19:1)
Address
Register
Write
Reg
512K x 18 Array
Write
Reg
512K x 18 Array
18
CLK
Gen.
Output
Logic
Control
R/W
C
C
CQ
DOFF
Read Data Reg.
36
18
Control
Logic
18
Reg.
Reg.
Reg. 18
V
REF
R/W
BWS
[1:0]
CQ
18
DQ
[17:0]
18
Logic Block Diagram (CY7C1318JV18)
A0
Burst
Logic
A
(18:0)
19
LD
K
K
18
Write Add. Decode
Read Add. Decode
A
(18:1)
Address
Register
Write
Reg
256K x 36 Array
Write
Reg
256K x 36 Array
36
CLK
Gen.
Output
Logic
Control
R/W
C
C
CQ
DOFF
Read Data Reg.
72
36
Control
Logic
36
Reg.
Reg.
Reg. 36
V
REF
R/W
BWS
[3:0]
CQ
36
DQ
[35:0]
36
Document Number: 001-15271 Rev. *E
Page 2 of 24
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CY7C1318JV18
CY7C1320JV18
Pin Configuration
The pin configuration for CY7C1318JV18, and CY7C1320JV18 follows.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1318JV18 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1320JV18 (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
NC/144M NC/36M
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-15271 Rev. *E
Page 3 of 24
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CY7C1318JV18
CY7C1320JV18
Pin Definitions
Pin Name
DQ
[x:0]
IO
Input Output-
Synchronous
Pin Description
Data Input Output Signals.
Sampled on the rising edge of K and K clocks during valid write operations.
These pins drive out the requested data during a read operation. Valid data is driven out on the rising
edge of both the C and C clocks during read operations or K and K when in single clock mode. When
read access is deselected, Q
[x:0]
are automatically tri-stated.
CY7C1318JV18
−
DQ
[17:0]
CY7C1320JV18
−
DQ
[35:0]
Synchronous Load.
This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data.
Byte Write Select 0, 1, 2, and 3
−
Active LOW.
Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the Write
operations. Bytes not written remain unaltered.
CY7C1318JV18
−
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1320JV18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs.
These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 1M x 18 (2 arrays each of 512K x 18) for CY7C1318JV18, and 512K x 36 (2 arrays
each of 256K x 36) for CY7C1320JV18.
CY7C1318JV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.
20 address inputs are needed to access the entire memory array.
CY7C1320JV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.
19 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.
Synchronous Read/Write Input.
When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
Positive Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See
Application Example
on page 7 for more information.
Negative Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See
Application Example
on page 7 for more information.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative Input Clock Input.
K is used to capture synchronous data being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
CQ is Referenced With Respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
Switching Characteristics
on page 21.
CQ is Referenced With Respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
Switching Characteristics
on page 21.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin is connected directly to V
DDQ
, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
LD
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
Input-
Synchronous
Input-
Synchronous
A, A0
Input-
Synchronous
R/W
Input-
Synchronous
Input Clock
C
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Output Clock
CQ
Output Clock
ZQ
Input
Document Number: 001-15271 Rev. *E
Page 4 of 24
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CY7C1318JV18
CY7C1320JV18
Pin Definitions
Pin Name
DOFF
Input
IO
(continued)
Pin Description
DLL Turn Off
−
Active LOW.
Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this
pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR I
mode when the DLL is turned off. In this mode, the device is operated at a frequency of up to 167 MHz
with DDR I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
Output
Input
Input
Input
N/A
N/A
N/A
NC/144M N/A
NC/288M N/A
V
REF
V
DD
V
SS
V
DDQ
Input-
Reference
Power Supply
Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply
Power Supply Inputs for the Outputs of the Device.
Document Number: 001-15271 Rev. *E
Page 5 of 24
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