Lead-
Free
Package
Options
Available!
ispLSI 1032E
®
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0
D Q
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
C7
Output Routing Pool
A2
A3
A4
A5
A6
A7
D Q
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE
TECHNOLOGY
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
E
2
CMOS
®
D Q
D Q
ES
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
D
EW
Output Routing Pool
0139A(A1)-isp
— Reprogram Soldered Devices for Faster Prototyping
— Four Dedicated Clock Input Pins
03
— Enhanced Pin Locking Capability
2E
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-vola-
tile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
U
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
pL
S
— Programmable Output Slew Rate Control to
Minimize Switching Noise
I1
— Synchronous and Asynchronous Clocks
A
FO
R
N
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1032e_09
1
IG
C3
C2
C1
C0
Logic
Array
C5
GLB
C4
CLK
N
August 2006
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
Output Routing Pool
A1
C6
S
Specifications
ispLSI 1032E
Functional Block Diagram
Figure 1. ispLSI 1032E Functional Block Diagram
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 7
IN 6
RESET
Input Bus
D7
D6
D5
D4
D3
D2
D1
D0
C7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
A0
A1
Output Routing Pool (ORP)
C6
Output Routing Pool (ORP)
A3
A4
A5
A6
A7
EW
Global
Routing
Pool
(GRP)
C4
C3
C2
C1
C0
lnput Bus
lnput Bus
A2
D
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
C5
N
B0
B1
B2
B3
FO
B4
B5
R
B6
B7
Clock
Distribution
Network
Output Routing Pool (ORP)
2E
ispEN
SDO/IN 2
SCLK/IN 3
A
Megablock
Input Bus
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1032E device contains four Megablocks.
U
SE
is
p
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
03
LS
I1
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1032E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032E device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
2
I/O 28
I/O 29
I/O 30
I/O 31
Y0
Y1
Y2
Y3
ES
IG
GOE 1/IN 5
GOE 0/IN 4
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
N
Generic
Logic Blocks
(GLBs)
Output Routing Pool (ORP)
S
Specifications
ispLSI 1032E
Absolute Maximum Ratings
1
Supply Voltage V
cc
...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
EW
D
MIN.
4.75
4.5
0
2.0
MAX.
5.25
5.5
0.8
V
cc
+1
UNITS
V
V
V
V
Table 2-0005/1032E
V
CC
V
IL
V
IH
T
A
= 0°C to + 70°C
2E
A
Capacitance (T
A
=25
o
C, f=1.0 MHz)
SYMBOL
PARAMETER
FO
R
T
A
= -40°C to + 85°C
N
TYPICAL
8
15
UNITS
pf
pf
C
2
03
C
1
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
Y0 Clock Capacitance
LS
I1
Data Retention Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008/1032E
U
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Data Retention
3
ES
IG
Case Temp. with Power Applied .............. -55 to 125°C
TEST CONDITIONS
V
CC
= 5.0V, V
PIN
= 2.0V
V
CC
= 5.0V, V
PIN
= 2.0V
Table 2-0006/1032E
N
S
Specifications
ispLSI 1032E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
-125
Others
1.5V
1.5V
See Figure 2
Table 2-0003/1032E
Figure 2. Test Load
≤
2 ns
≤
3 ns
+ 5V
R1
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
EW
D
ES
IG
R2
CL
*
MIN.
–
2.4
–
–
–
–
–
Commercial
Industrial
–
–
TYP.
–
–
–
–
–
–
–
190
190
3
Device
Output
N
0.4
–
-10
10
-150
-150
-200
–
–
C
DC Electrical Characteristics
SYMBOL
2E
A
Over Recommended Operating Conditions
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
MAX. UNITS
V
V
μA
μA
μA
μA
mA
mA
mA
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
LS
I1
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
Input or I/O Low Leakage Current
Operating Power Supply Current
is
p
03
FO
Table 2-0004/1032E
R
N
Table 2-0007/1032E
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
U
SE
4
S
Test
Point
0213a
Specifications
ispLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.
4
#
2
DESCRIPTION
1
-125
–
–
125
1
-100
–
–
100
71.0
125
7.0
–
10.0
12.5
–
–
MIN. MAX. MIN. MAX.
7.5
10.0
–
–
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
03
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
1.
2.
3.
4.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
–
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
(
tsu2 + tco1
)
Clock Frequency, Max. Toggle
(
1
twh + tw1
)
167
5.0
–
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
D
6.0
–
0.0
–
5.0
–
–
–
–
3.0
3.0
3.0
0.0
0.0
EW
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
N
R
FO
A
18 External Synchronous Clock Pulse Duration, High
2E
19 External Synchronous Clock Pulse Duration, Low
20
21
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
U
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LS
I1
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
ES
IG
5.0
–
–
6.0
–
10.0
–
12.0
12.0
7.0
7.0
–
–
–
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
4.0
4.0
3.5
0.0
91.0
N
–
–
6.0
–
–
7.0
–
13.5
–
15.0
15.0
9.0
9.0
–
–
–
–
Table 2-0030A/1032E
S
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