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ADS1282
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
ADS1282 High-Resolution Analog-To-Digital Converter
1 Features
1
3 Description
The ADS1282 is an extremely high-performance,
single-chip analog-to-digital converter (ADC) with an
integrated, low-noise programmable gain amplifier
(PGA) and two-channel input multiplexer (mux). The
ADS1282 is suitable for the demanding needs of
energy
exploration
and
seismic
monitoring
environments.
The converter uses a fourth-order, inherently stable,
delta-sigma (ΔΣ) modulator that provides outstanding
noise and linearity performance. The modulator is
used either in conjunction with the on-chip digital
filter, or can be bypassed for use with post
processing filters.
The flexible input MUX provides an additional
external input for measurement, as well as internal
self-test connections. The PGA features outstanding
low noise (5 nV/√Hz) and high input impedance,
allowing easy interfacing to geophones and
hydrophones over a wide range of gains.
The digital filter provides selectable data rates from
250 to 4000 samples per second (SPS). The high-
pass filter (HPF) features an adjustable corner
frequency. On-chip gain and offset scaling registers
support system calibration.
The synchronization input (SYNC) can be used to
synchronize the conversions of multiple ADS1282s.
The SYNC input also accepts a clock input for
continuous alignment of conversions from an external
source.
Together, the amplifier, modulator, and filter dissipate
25 mW. The ADS1282 is available in a compact
TSSOP-28 package and is fully specified from –40°C
to +85°C, with a maximum operating range to
+125°C.
•
•
•
•
•
•
•
•
•
•
•
•
High Resolution:
130-dB SNR (250 SPS)
High Accuracy:
THD: –122 dB
INL: 0.5 ppm
Low-Noise PGA
Two-Channel Input Mux
Inherently-Stable Modulator with Fast Responding
Overrange Detection
Flexible Digital Filter:
Sinc + FIR + IIR (Selectable)
Linear or Minimum Phase Response
Programmable High-Pass Filter
Selectable FIR Data Rates: 250 SPS to 4 kSPS
Filter Bypass Option
Low Power Consumption: 25 mW
Shutdown: 10
μW
Offset and Gain Calibration Engine
SYNC Input
Analog Supply:
Unipolar (+5 V) or Bipolar (±2.5 V)
Digital Supply: 1.8 V to 3.3 V
2 Applications
•
•
•
Energy Exploration
Seismic Monitoring
High-Accuracy Instrumentation
AVDD
VREFN
VREFP
DVDD
ADS1282
CLK
SCLK
DOUT
DIN
DRDY
Input 1
Input 2
V
COM
Over-Range
Modulator Output
PGA
4th-Order
DS
Modulator
MUX
Programmable
Digital Filter
Calibration
SPI
Interface
Control
3
SYNC
RESET
PWDN
AVSS
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1282
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
4 Ordering Information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at
ti.com.
5 Specifications
5.1
Absolute Maximum Ratings
(1)
ADS1282, ADS1282H
AVDD to AVSS
AVSS to DGND
DVDD to DGND
Input current
Input current
Analog input voltage
Digital input voltage to DGND
Maximum junction temperature
Operating temperature range
Storage temperature range
(1)
–0.3 to +5.5
–2.8 to +0.3
–0.3 to +3.9
100, momentary
10, continuous
AVSS – 0.3 to AVDD + 0.3
–0.3 to DVDD + 0.3
+150
–40 to +125
–60 to +150
UNIT
V
V
V
mA
mA
V
V
°C
°C
°C
Over operating free-air temperature range (unless otherwise noted).
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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ADS1282
Copyright © 2007–2015, Texas Instruments Incorporated
ADS1282
www.ti.com
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
5.2 Electrical Characteristics
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, f
CLK (1)
= 4.096MHz,
VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, and f
DATA
= 1000SPS, unless otherwise
noted.
PARAMETER
ANALOG INPUTS
Full-scale input voltage
Absolute input range
PGA input voltage noise density
Differential input impedance
Common-mode input impedance
Input bias current
Crosstalk
MUX on-resistance
PGA OUTPUT (CAPP, CAPN)
Absolute output range
PGA differential output impedance
Output impedance tolerance
External bypass capacitance
Modulator differential input impedance
AC PERFORMANCE
Signal-to-noise ratio
(2)
(3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IN
= (AINP – AINN)
AINP or AINN
AVSS + 0.7
±V
REF
/(2 × PGA)
AVDD – 1.25
5
V
V
nV/√Hz
GΩ
GΩ
MΩ
nA
dB
Ω
Chop on
Chop off
1
100
100
1
f = 31.25Hz
–135
30
AVSS + 0.4
600
±10%
10
55
AVDD – 0.4
V
Ω
100
nF
kΩ
SNR
PGA = 1...16
120
124
–122
–117
–115
123
–114
–110
dB
Total harmonic distortion
THD
PGA = 32
PGA = 64
dB
Spurious-free dynamic
range
DC PERFORMANCE
Resolution
Data rate
Integral nonlinearity (INL)
Offset error
Offset error after calibration
Offset drift
Gain error
(7)
(6)
(4)
SFDR
dB
No missing codes
f
DATA
FIR filter mode
Sinc filter mode
Differential input
31
250
8000
0.00005
50
4000
128,000
0.0004
200
Bits
SPS
SPS
% FSR
(5)
μV
μV
μV/°C
–0.5%
Shorted input
1
0.02
–1.5%
–1.0%
0.0002%
Gain error after calibration
(6)
Gain drift
Gain matching
(8)
PGA = 1
PGA = 16
f
CM
= 60Hz
(9)
AVDD, AVSS
DVDD
f
PS
= 60Hz
(9)
2
9
0.3%
95
80
90
110
90
115
0.8%
ppm/°C
ppm/°C
Common-mode rejection
Power-supply rejection
dB
dB
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
f
CLK
= system clock.
V
IN
= 20mV
DC
/PGA; see
Table 1.
V
IN
= 31.25Hz, –0.5dBFS.
Best-fit method.
FSR: Full-scale range = ±V
REF
/(2 × PGA).
Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
Gain match relative to PGA = 1.
f
CM
is the input common-mode frequency. f
PS
is the power-supply frequency.
Copyright © 2007–2015, Texas Instruments Incorporated
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ADS1282
3
ADS1282
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
www.ti.com
Electrical Characteristics (continued)
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, f
CLK (1)
= 4.096MHz,
VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, and f
DATA
= 1000SPS, unless otherwise
noted.
PARAMETER
VOLTAGE REFERENCE INPUTS
Reference input voltage
Negative reference input
Positive reference input
Reference input impedance
DIGITAL FILTER RESPONSE
Passband ripple
Passband (–0.01dB)
Bandwidth (–3dB)
High-pass filter corner
Stop band attenuation
Stop band
Group delay
Minimum phase filter
(11)
Linear phase filter
Minimum phase filter
Linear phase filter
(10)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(V
REF
= VREFP – VREFN)
VREFN
VREFP
0.5
AVSS – 0.1
VREFN + 0.5
5
(AVDD – AVSS)
+ 0.2
VREFP – 0.5
AVDD + 0.1
V
V
V
kΩ
85
±0.003
0.375 × f
DATA
0.413 × f
DATA
0.1
135
0.500 × f
DATA
5/f
DATA
31/f
DATA
62/f
DATA
62/f
DATA
0.8 × DVDD
DGND
I
OH
= 1mA
I
OL
= 1mA
0 < V
DIGITAL IN
< DVDD
f
CLK
f
SCLK
–2.6
AVSS + 4.75
1.65
Normal operation
4.5
1
1
0.6
0.1
25
(12)
dB
Hz
Hz
10
Hz
dB
Hz
s
Settling time (latency)
DIGITAL INPUT/OUTPUT
V
IH
V
IL
V
OH
V
OL
Input leakage
Clock input
Serial clock rate
POWER SUPPLY
AVSS
AVDD
DVDD
s
DVDD
0.2 × DVDD
V
V
V
0.8 × DVDD
0.2 × DVDD
±10
1
4.096
f
CLK
/2
0
AVSS + 5.25
3.6
6.5
15
15
0.8
V
μA
MHz
MHz
V
V
V
|mA|
|μA|
|μA|
mA
mA
AVDD, AVSS current
Standby mode
Power-down mode
Normal operation
DVDD current
Modulator mode
Standby mode
Power-down mode
50
15
35
250
125
μA
μA
mW
μW
μW
1
25
90
10
Normal operation
Power dissipation
Standby mode
Power-down mode
(10) Input frequencies in the range of Nf
CLK
/512 ± f
DATA
/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120dB, typ.
(11) At dc; see
Figure 44.
(12) CLK input stopped.
4
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ADS1282
Copyright © 2007–2015, Texas Instruments Incorporated
ADS1282
www.ti.com
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
6 Timing Diagram
t
SCLK
SCLK
t
DIST
DIN
t
DIHD
DOUT
t
DOPD
t
DOHD
t
SPWL
t
SCDL
t
SCDL
t
SPWH
6.1
Timing Requirements
MIN
2
0.8
50
50
(2)
At T
A
= –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted.
PARAMETER DESCRIPTION
t
SCLK
t
SPWH, L
t
DIST
t
DIHD
t
DOPD
t
DOHD
t
SCDL
(1)
(2)
SCLK period
SCLK pulse width, high and low
(1)
DIN valid to SCLK rising edge: setup time
Valid DIN to SCLK rising edge: hold time
SCLK falling edge to valid new DOUT: propagation delay
SCLK falling edge to DOUT invalid: hold time
Final SCLK rising edge of command to first SCLK rising edge for register read/write
data. (Also between consecutive commands.)
MAX
16
10
UNITS
1/f
CLK
1/f
CLK
ns
ns
100
0
24
ns
ns
1/f
CLK
Holding SCLK low for 64 DRDY falling edges resets the serial interface.
Load on DOUT = 20pF || 100kΩ.
Copyright © 2007–2015, Texas Instruments Incorporated
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5
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