CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Features
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Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140
[1]
and CY7C141
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
1K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: I
CC
= 110 mA (maximum)
Fully asynchronous operation
Automatic power down
Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
INT flag for port-to-port communication
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
Pb-free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
I/O
7L
I/O
0L
BUSY
L
I/O
CONTROL
I/O
CONTROL
I/O
7R
I/O
0R
BUSY
R
[2]
A
9L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
9R
A
0R
CE
L
OE
L
R/W
L
INT
L
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CE
R
OE
R
R/W
R
INT
R
[3]
[3]
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06002 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 09, 2008
[+] Feedback
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Pin Configurations
Figure 1. Pin Diagram - DIP (Top View)
CE
L
R/W
L
BUSY
L
INT
L
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
12 7C130 37
13 7C140 36
14
35
15
34
16
33
17
32
18
31
30
19
20
29
28
21
22
27
23
26
24
25
V
CC
CE
R
R/W
R
BUSY
R
INT
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
Figure 2. Pin Diagram - PLCC (Top View)
BUSY
R
INTR
NC
BUSYL
R/W
L
CEL
VCC
CER
R/W
R
A0L
OEL
NC
INT
L
Figure 3. Pin Diagram - PQFP (Top View)
BUSY
R
INTR
NC
BUSYL
R/W
L
CEL
VCC
A0L
OEL
NC
INT
L
CER
R/W
R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
8
9
10
11
12
13
14
15
16
17
18
19
20
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C131
40
7C141
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
52 5150 49 48 47 4645 44 43 42 41 40
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
7C131
7C141
1415 16 17 18 19 20 21 22 23 24 25 26
NC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
Document #: 38-06002 Rev. *E
I/O5R
I/O6R
I/O4L
I/O5L
I/O6L
I/O7L
Page 2 of 19
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CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Maximum Ratings
[5]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150
°
C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)............................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ............................................–3.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
[6]
Ambient Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V ± 10%
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
[7]
7C130-30
[4]
7C131-15
7C130A-30
7C131A-15 7C131-25,30
7C141-15
7C140-30
7C141-25,30
Min Max Min Max
2.4
2.4
0.4
0.4
0.5
0.5
2.2
2.2
0.8
0.8
–5
+5
–5
+5
–5
+5
–5
+5
[4]
Parameter
Description
Test Conditions
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
Min
2.4
Max
0.4
0.5
2.2
–5
–5
0.8
+5
+5
–350
120
45
90
7C130-55
7C131-55
7C140-55
7C141-55
Min
2.4
Max
0.4
0.5
2.2
–5
–5
0.8
+5
+5
Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage
Current
Output Short
Circuit Current
[9, 10]
V
CC
Operating
Supply Current
Standby Current
Both Ports, TTL Inputs
Standby Current
One Port,
TTL Inputs
Standby Current
Both Ports,
CMOS Inputs
Standby Current
One Port,
CMOS Inputs
V
CC
= Min, I
OH
= –4.0 mA
I
OL
= 4.0 mA
I
OL
= 16.0 mA
[8]
V
V
V
V
μA
μA
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max,
V
OUT
= GND
CE = V
IL
,
Com’l
[11]
Outputs Open, f = f
MAX
CE
L
and CE
R
> V
IH
,
Com’l
[11]
f = f
MAX
CE
L
or CE
R
> V
IH
,
Com’l
Active Port Outputs Open
f = f
MAX[11]
Both Ports CE
L
and CE
R
> Com’l
V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
One Port CE
L
or
Com’l
CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V,
Active Port Outputs Open, f =
f
MAX[11]
–350
190
75
135
–350
170
65
115
–350 mA
110
35
75
mA
mA
mA
I
SB3
15
15
15
15
mA
I
SB4
125
105
85
70
mA
Shaded areas contain preliminary information.
Notes
5. The voltage on any input or I/O pin cannot exceed the power pin during power up.
6. T
A
is the “instant on” case temperature
7. See the last page of this specification for Group A subgroup testing information.
8. BUSY and INT pins only.
9. Duration of the short circuit should not exceed 30 seconds.
10. This parameter is guaranteed but not tested.
11. At f = f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
RC
and using AC Test Waveforms input levels of GND to 3V.
Document #: 38-06002 Rev. *E
Page 4 of 19
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