November 2007
IMSH51U03A1F1C
IMSH51E03A1F1C
IMSH1GU13A1F1C
IMSH1GE13A1F1C
240-Pin DDR3 Unbuffered Memory Modules
5 1 2 M B , 1G B
RoHS Compliant
Advance
Internet Data Sheet
Rev. 0.54
Advance Internet Data Sheet
IMSH[51/1G][U/E]xxA1F1C
DDR3 Unbuffered DIMM
IMSH51U03A1F1C, IMSH51E03A1F1C, IMSH1GU13A1F1C
Revision History: 2007-11, Rev. 0.54
Page
All
Subjects (major changes since last revision)
Editorial changes.
Previous Revision: Rev. 0.53, 2007-11
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11202007-PQTI-I4UF
2
Advance Internet Data Sheet
IMSH[51/1G][U/E]xxA1F1C
DDR3 Unbuffered DIMM
1
Overview
This chapter gives an overview of the 240–pin Unbuffered DDR3 Dual-In-Line Memory Modules product family and describes
its main characteristics.
1.1
Features
• Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
• On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
• Refresh. Self Refresh and Power Down Modes.
• ZQ Calibration for output driver and ODT.
• System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
• Serial Presence Detect with EEPROM.
• UDIMM dimensions: 133.35 mm x 30 mm.
• Based on standard reference raw cards: 'A', 'B', 'D' and 'E'
• RoHS compliant products
1)
.
• 240-pin 8-Byte DDR3 SDRAM Unbuffered Dual-In-Line
Memory Modules .
• Module organization: 128M
×
64, 128M
×
72, 64M
×
64,
64M
×
72
Chip organization: 64M
×
8.
• PC3-12800, PC3-10600, PC3-8500 and PC3-6400
module speed grades.
• 1GB, 512MB modules built with 512Mb DDR3 SDRAMs in
packages PG-TFBGA-78
• DDR3 SDRAMs with a single 1.5 V (± 0.075 V) power
supply.
• Asynchronous Reset.
TABLE 1
Performance Table for DDR3–1600 and DDR3–1333
Qimonda Speed Code
Module Speed Bin
Device Speed Bin
CL-
n
RCD
-
n
RP
CL and CWL settings for
maximum clock frequency
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
PC3
DDR3
–16H
–12800H
–1600H
9-9-9
CL = 9
CWL = 8
800
1600
667
1333
–16J
–12800J
–1600J
10-10-10
CL = 10
CWL = 8
800
1600
667
1333
–13G
–10600G
–1333G
8-8-8
CL = 8
CWL = 7
667
1333
533
1066
–13H
–10600H
–1333H
9-9-9
CL = 9
CWL = 7
667
1333
533
1066
–13J
–10600J
–1333J
10-10-10
CL = 10
CWL = 7
667
1333
533
1066
MHz
MHz
Mb/s
MHz
Mb/s
Unit
Note
1)
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to
Chapter 4.1
Speed Bins.
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 0.54, 2007-11
11202007-PQTI-I4UF
3
Advance Internet Data Sheet
IMSH[51/1G][U/E]xxA1F1C
DDR3 Unbuffered DIMM
TABLE 2
Performance Table for DDR3–1066 and DDR3–800
Qimonda Speed Code
Module Speed Bin
Device Speed Bin
CL-
n
RCD
-
n
RP
CL and CWL settings for
maximum clock frequency
Maximum Clock Frequency
and Data Rate
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
with above CL and CWL settings
PC3
DDR3
–10E
–8500E
–1066E
6-6-6
CL = 6
CWL = 6
533
1066
400
800
–10F
–8500F
–1066F
7-7-7
CL = 7
CWL = 6
533
1066
400
800
–10G
–8500G
–1066G
8-8-8
CL = 8
CWL = 6
533
1066
400
800
–08D
–6400D
–800D
5-5-5
CL = 5
CWL = 5
400
800
300
600
–08E
–6400E
–800E
6-6-6
CL = 6
CWL = 5
400
800
300
600
MHz
MHz
Mb/s
MHz
Mb/s
Unit
Note
1)
1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to
Chapter 4.1
Speed Bins.
Rev. 0.54, 2007-11
11202007-PQTI-I4UF
4
Advance Internet Data Sheet
IMSH[51/1G][U/E]xxA1F1C
DDR3 Unbuffered DIMM
1.2
Description
The memory array is designed with 512Mb Double Data Rate
(DDR3) Synchronous DRAMs. De-coupling capacitors, stub
resistors, calibration resistors and termination resistors are
mounted on the PCB board. The DIMMs feature serial
presence detect based on a 256 byte serial EEPROM device
using the 2-pin I2C protocol. The first 176 bytes are
programmed with module specific SPD data.
The Qimonda IMSH[51/1G][U/E]xxA1F1C are Unbuffered
DIMM (UDIMM) family with 30 mm height based on DDR3
SDRAM technology.
DIMMs are available non-ECC modules in128M
×
64 (1GB),
64M
×
64 (512MB)
and
as
ECC
modules
in
128M
×
72 (1GB), 64M
×
72 (512MB) organization and
density, intended for mounting into 240 pin connector
sockets.
TABLE 3
Ordering Information Table
Qimonda Part Number
IMSH51U03A1F1C–08D
IMSH51U03A1F1C–08E
IMSH51U03A1F1C–10E
IMSH51U03A1F1C–10F
IMSH51U03A1F1C–10G
IMSH51U03A1F1C–13G
IMSH51U03A1F1C–13H
IMSH51U03A1F1C–13J
IMSH51U03A1F1C–16H
IMSH51U03A1F1C–16J
Compliance Code
512MB 1R×8 PC3–6400U–5-XX–A0
512MB 1R×8 PC3–6400U–6-XX–A0
512MB 1R×8 PC3–8500U–6-XX–A0
512MB 1R×8 PC3–8500U–7-XX–A0
512MB 1R×8 PC3–8500U–8-XX–A0
512MB 1R×8 PC3–10600U–8-XX–A0
512MB 1R×8 PC3–10600U–9-XX–A0
512MB 1R×8 PC3–10600U–10-XX–A0
512MB 1R×8 PC3–12800U–9-XX–A0
512MB 1R×8 PC3–12800U–10-XX–A0
Description
240-pin 512 MByte DDR3 Unbuffered DIMM with
one rank for non-ECC applications. The memory
rank consists of eight DDR3 components in x8
organization. Standard reference card A is used on
this assembly.
Used DDR3 SDRAM Component
Part Number: IDSH51-03A1F1C
Density: 512 Mbit
Organization: 64Mbit × 8
Address Bits (Row/Column/Bank): 13/10/3
512 MByte Non-ECC Unbuffered DIMM IMSH51U03A1F1C
512 MByte ECC Unbuffered DIMM IMSH51E03A1F1C
IMSH51E03A1F1C–08D
IMSH51E03A1F1C–08E
IMSH51E03A1F1C–10E
IMSH51E03A1F1C–10F
IMSH51E03A1F1C–10G
IMSH51E03A1F1C–13G
IMSH51E03A1F1C–13H
IMSH51E03A1F1C–13J
IMSH51E03A1F1C–16H
IMSH51E03A1F1C–16J
512MB 1R×8 PC3–6400E–5-XX–D0
512MB 1R×8 PC3–6400E–6-XX–D0
512MB 1R×8 PC3–8500E–6-XX–D0
512MB 1R×8 PC3–8500E–7-XX–D0
512MB 1R×8 PC3–8500E–8-XX–D0
512MB 1R×8 PC3–10600E–8-XX–D0
512MB 1R×8 PC3–10600E–9-XX–D0
512MB 1R×8 PC3–10600E–10-XX–D0
512MB 1R×8 PC3–12800E–9-XX–D0
512MB 1R×8 PC3–12800E–10-XX–D0
240-pin 512 MByte DDR3 Unbuffered DIMM with
one rank for ECC applications. The memory rank
consists of nine DDR3 components in x8
organization. Standard reference card D is used on
this assembly.
Used DDR3 SDRAM Component
Part Number: IDSH51-03A1F1C
Density: 512 Mbit
Organization: 64Mbit × 8
Address Bits (Row/Column/Bank): 13/10/3
Rev. 0.54, 2007-11
11202007-PQTI-I4UF
5
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