PRELIMINARY
CY7C1303AV25
CY7C1306AV25
18-Mb Burst of 2 Pipelined SRAM with
QDR™ Architecture
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix) Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
• Variable Impedance HSTL
Functional Description
The CY7C1303AV25 and CY7C1306AV25 are 2.5V
Synchronous Pipelined SRAMs equipped with QDR™ archi-
tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K clock.
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303AV25/
CY7C1306AV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing perfor-
mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7C1303AV25) or two
36-bit words (CY7C1306AV25) that burst sequentially into or
out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1303AV25 – 1M x 18
CY7C1306AV25 – 512K x 36
Logic Block Diagram (CY7C1303AV25)
D
[17:0]
18
Write
Data Reg
Write Add. Decode
Write
Data Reg
Read Add. Decode
A
(18:0)
Address
Register
19
K
K
CLK
Gen.
512Kx18
Memory
Array
512Kx18
Memory
Array
Address
Register
19
A
(18:0)
Control
Logic
RPS
C
C
Read Data Reg.
36
Vref
WPS
BWS
0
BWS
1
Cypress Semiconductor Corporation
Document #: 38-05493 Rev. *A
•
3901 North First Street
•
Control
Logic
18
18
Reg.
Reg.
18
Reg. 18
18
Q
[17:0]
San Jose
,
CA 95134
•
408-943-2600
Revised June 1, 2004
PRELIMINARY
Logic Block Diagram (CY7C1306AV25)
D
[35:0]
36
Write
Data Reg
Write Add. Decode
Write
Data Reg
Read Add. Decode
CY7C1303AV25
CY7C1306AV25
A
(17:0)
Address
Register
18
K
K
CLK
Gen.
256Kx36
Memory
Array
256Kx36
Memory
Array
Address
Register
18
A
(17:0)
Control
Logic
RPS
C
C
Read Data Reg.
72
Vref
WPS
BWS
0
BWS
1
BWS
2
BWS
3
Control
Logic
36
36
Reg.
Reg.
36
Reg. 36
36
Q
[35:0]
Selection Guide
CY7C1303AV25-167 CY7C1303AV25-133 CY7C1303AV25-100
CY7C1306AV25-167 CY7C1306AV25-133 CY7C1306AV25-100
Maximum Operating Frequency
Maximum Operating Current
167
750
133
650
100
550
Unit
MHz
mA
Pin Configuration – CY7C1303AV25 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
Gnd/
144M
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/ 36M
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS
1
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
NC
BWS
0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
Gnd/
72M
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Document #: 38-05493 Rev. *A
Page 2 of 19
PRELIMINARY
Pin Configuration - CY7C1306AV25 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
Q27
D27
D28
Q29
Q30
D30
NC
D31
Q32
Q33
D33
D34
Q35
TDO
2
Gnd/
288M
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC/ 72M
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS
2
BWS
3
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
C
7
BWS
1
BWS
0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
CY7C1303AV25
CY7C1306AV25
9
NC/36M
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
A
10
Gnd/
144M
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Pin Definitions
Name
D
[x:0]
I/O
Input-
Synchronous
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1303AV25 – D
[17:0]
CY7C1306AV25 – D
[35:0]
Write Port Select, active LOW.
Sampled on the rising edge of the K clock. When as-
serted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
[x:0]
to be ignored.
Byte Write Select 0, 1, 2 and 3 - active LOW.
Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations.
CY7C1303AV25 - BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1306AV25 - BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the cor-
responding byte of data to be ignored and not written into the device.
Address Inputs.
Sampled on the rising edge of the K clock during active Read opera-
tions and on the rising edge of K for Write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 1M x
18 (2 arrays each of 512K x 18) for CY7C1303AV25 and 512K x 36 (2 arrays each of
256K x 36) for CY7C1306AV25. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1303AV25 and 18 address inputs for CY7C1306AV25.
These inputs are ignored when the appropriate port is deselected.
Data Output signals.
These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q
[x:0]
are automatically three-stated.
CY7C1303AV25 - Q
[17:0]
CY7C1306AV25 - Q
[35:0]
Read Port Select, active LOW.
Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the K clock. Each
read access consists of a burst of two sequential 18-bit or 36-bit transfers.
WPS
Input-
Synchronous
Input-
Synchronous
BWS
0
, BWS
1
,
BWS
2
, BWS
3
A
Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS
Input-
Synchronous
Document #: 38-05493 Rev. *A
Page 3 of 19
PRELIMINARY
Pin Definitions
(continued)
Name
C
I/O
Input-Clock
Description
CY7C1303AV25
CY7C1306AV25
Positive Output Clock Input.
C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input.
C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs to the device and
to drive out data through Q
[x:0]
when in single clock mode.
Output Impedance Matching Input.
This input is used to tune the device outputs to the
system data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to V
DD
, which enables the minimum impedance mode. This pin cannot be con-
nected directly to GND or left unconnected.
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 36M.
This pin is not connected to the die and so can be tied to
any voltage level on CY7C1303AV25/CY7C1306AV25.
Address expansion for 72M.
This pin has to be tied to GND on CY7C1303AV25.
Address expansion for 72M.
This pin can be tied to any voltage level on
CY7C1306AV25.
Address expansion for 144M.
This pin has to be tied to GND on
CY7C1303AV25/CY7C1306AV25.
Address expansion for 288M.
This pin has to be tied to GND on CY7C1306AV25.
Not connected to the die.
Can be tied to any voltage level.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
enced from the rising edge of the input clocks (K and K) and
all output timings are referenced to rising edge of output clocks
(C and C or K and K when in single clock mode).
All synchronous data inputs (D
[x:0]
) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q
[x:0]
) pass through
output registers controlled by the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS
[x:0]
) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
The following descriptions take CY7C1303AV25 as an
example. The same basic descriptions apply to
CY7C1306AV25.
Read Operations
The CY7C1303AV25 is organized internally as 2 arrays of
512K x 18. Accesses are completed in a burst of two
Page 4 of 19
C
Input-Clock
K
Input-Clock
K
ZQ
Input-Clock
Input
TDO
TCK
TDI
TMS
NC/36M
GND/72M
NC/72M
GND/144M
GND/288M
NC
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
N/A
Input
N/A
Input
Input
N/A
Input-
Reference
Power Supply
Ground
Power Supply
Introduction
Functional Overview
The CY7C1303AV25/CY7C1306AV25 are synchronous
pipelined Burst SRAM equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, this architecture completely
eliminates the need to “turn-around” the data bus and avoids
any possible data contention, thereby simplifying system
design. Each access consists of two 18-bit data transfers in
the case of CY7C1303AV25, and two 36-bit data transfers in
the case of CY7C1306AV25, in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer-
Document #: 38-05493 Rev. *A
PRELIMINARY
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q
[17:0]
using C as
the output timing reference. On the subsequent rising edge of
C the higher order data word is driven onto the Q
[17:0]
. The
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C, or K and K when in single clock mode,
167-MHz device).
Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D
[17:0]
is latched and stored into the
lower 18-bit Write Data register provided BWS
[1:0]
are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D
[17:0]
is stored into the Write Data register
provided BWS
[1:0]
are both asserted active. The 36 bits of data
are then written into the memory array at the specified
location.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1303AV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS
0
and BWS
1
which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
CY7C1303AV25
CY7C1306AV25
The CY7C1303AV25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-up.This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1303AV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1303AV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
SS
to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
,
with
V
DDQ
=1.5V. The output impedance is adjusted every 1024
cycles to account for drifts in supply voltage and temperature.
Application Example
[1]
Note:
1. The above application shows 4 QDR-I being used.
Document #: 38-05493 Rev. *A
Page 5 of 19
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