SDC-14532 MONOBRID SERIES
12- AND 14-BIT SYNCHRO-TO-DIGITAL
OR RESOLVER-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
The SDC-14532 is a complete 12- or 14-
bit synchro-to-digital (S/D) or resolver-to-
digital (R/D) converter contained in a small
32-pin TDIP hybrid package. Features of
this series include ±5.3 minute accuracy,
an Inhibit input which, when applied, does
not interfere with tracking, and low power
consumption.
The SDC-14532 accepts broadband
inputs (360 to 2600 Hz), has solid-state
signals and reference isolation. The out-
put of the SDC-14532 is a natural binary
code, parallel positive logic and is CMOS
and TTL compatible.
•
Solid-State Inputs
•
MIL-PRF-38534 Screening
Available
•
Inhibit Does Not Interrupt
Tracking
•
Accuracy to ±5.3 Minutes
•
Three-State Latched Outputs
•
TTL and CMOS Compatible
•
Replacement for ANALOG’S
SDC-1740/1/2 Series and
NATEL’S HSD/HRD1114 and
1112
APPLICATIONS
With three-state outputs and an Inhibit that
does not stop the tracking process, the
SDC-14532 Series is especially well suit-
ed for bus multiplexing and microproces-
sor interfacing. These converters are ideal
for remotely located and hard to access
equipment where low power consumption
and small size are critical.
SOLID STATE SYNCHRO INPUT OPTION
SOLID STATE RESOLVER INPUT OPTION
S1
S2
S3
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
S4
RESOLVER
CONDITIONER
SIN
θ
COS
θ
INPUT OPTIONS
REF IN
RH
RL
BIT
REFERENCE
CONDITIONER
R
BIT DETECT
SIN
θ
INPUT OPTION
COS
θ
HIGH ACCURACY
CONTROL
TRANSFORMER
GAIN
SIN
(θ-φ)
DEMOD
D
ERROR
PROCESSOR
VEL
T
VCO
U
E
1 LSB ANTIJITTER FEEDBACK
16 BIT CT
TRANSPARENT
LATCH
U
50 ns DELAY
T
0.4-2 µs
CB
+5 V
DIGITAL
ANGLE
φ
16 BIT U-D
COUNTER
Q
INH
3 STATE
TTL BUFFER
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
INHIBIT
TRANSPARENT
LATCH
POWER
SUPPLY
CONDITIONER
INH
+10 V
INTERNAL DC
REF V (+5 V)
+15
EM
BITS 1-8
BITS 9-12 or 9-14
EL
S
FIGURE 1. SDC-14352 BLOCK DIAGRAM
© 1999 Data Device Corporation
TABLE 1. SDC-14532 SPECIFICATIONS
Apply over temperature range, power supply range, reference fre-
quency, and amplitude ranges: 10% signal amplitude variation; and
up to 10% harmonic distortion in reference.
PARAMETER
VALUE
RESOLUTION
12 or 14 bits
ACCURACY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Range
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(Voltage options and mini-
mum input impedance
balanced)
Synchro
Z
in
Line-to-Line
Z
in
Each Line to Ground
Resolver
Z
in
Single Ended
Z
in
Differential
Z
in
Each Line to Ground
Common Mode Range
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
±8.5 min (12 bit)
±5.3 min (14 bit)
TABLE 1. SDC-14532 SPECIFICATIONS (CONTINUED)
PARAMETER
VALUE
PHYSICAL
CHARACTERISTICS
Size
Weight
1.74 x 1.14 x 0.28 in.
(44 x 29 x 7.1 mm)
0.8 max (23 gm)
TECHNICAL INFORMATION
360 to 2600 Hz
4 to 130 Vrms
250k Ohm min
500k Ohm min
210 V peak max, 500 V transient peak
The information in this section describes the structures and
operation of the SDC-14532 Series.
INTRODUCTION
The circuit shown in the block diagram of Figure 1 contains two
main parts: a Feedback Loop, whose elements are the control
transformer, demodulator, error processor, VCO and up-down
counter; and Digital Interface circuitry including various latches
and buffers.
SIGNAL INPUTS
11.8 V L-L
17.5k Ohm
11.5k Ohm
11.8 V L-L
23k Ohm
46k Ohm
23k Ohm
25 V max
90 V L-L
130k Ohm
85k Ohm
26 V L-L
50k Ohm
100k Ohm
50k Ohm
60 V max
The SDC-14532 offers two input options: synchro or resolver. In
a synchro or resolver, shaft angle data is transmitted as the
ratio of carrier amplitudes across the input terminals. Synchro
signals, which are of the form sinθcosωt, sin(θ + 120°)cosωt,
and sin(θ +240°)cosωt are internally converted to resolver for-
mat; sinθcosωt and cosθcosωt (see FIGURE 2).
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection. Input
impedance is maintained with power off.
Inhibit (INH)
Enable bits 1 to 8 (EM)
Enable bits 9 to 12 (EL)
or bits 9 to 14
Output Parallel Data
Converter Busy (CB)
Drive Capability
TTL/CMOS compatible
Logic 0=0.8 V max
Logic 1=2.0 V min
Loading=30µA max pull-up current
source to +5V/5pF max, CMOS
transient protected.
Logic 0 inhibits, data stable after 0.5µs
Logic 0 enables, logic 1 high Z.
Logic 0 enables, logic 1 high Z.
12 or 14 parallel lines, natural binary
angle, positive logic.
0.4 to 2µs positive pulse; leading edge
initiates counter update.
50pF plus rated logic drive.
Logic 0: 1 TTL load, 1.6mA at 0.4V max
Logic 1: 10 TTL loads, 0.4mA at 2.8V
min.
High Z: 10µA//5pF max
Logic 1: +5V supply minus 100mV min
driving CMOS.
Logic 0 for fault condition
See Table 3.
FEEDBACK LOOP
The Feedback Loop produces a digital angle
φ
which tracks the
analog input angle
θ
to within the specified accuracy of the con-
verter. The control transformer performs the following trigono-
metric computation:
sin(θ
− φ)
= sinθ cosφ - cosθ sinφ
where:
θ
is the angle theta, representing the resolver shaft position.
φ
is the digital angle phi contained in the up/down counter.
The tracking process consists of continually adjusting
φ
to make
(θ
− φ) →
0, so that
φ
will represent the shaft position
θ.
The
output of the demodulator is an analog DC level proportional to
sin (θ
− φ).
The error processor receives its input from the
demodulator and integrates this sin(θ
− φ)
error signal which
then drives a Voltage-Controlled Oscillator (VCO). The VCO’s
clock pulses are accumulated by the up-down counter. The
velocity voltage accuracy, linearity and offset are determined by
the quality of the VCO. Functionally, the up-down counter is an
incremental integrator. Therefore, there are two stages of inte-
gration which make the converter a Type II tracking servo. In a
Type II servo, the VCO always settles to a counting rate which
makes dθ/dt without a lag. The output data will always be fresh
and available as long as the maximum tracking rate of the con-
verter is not exceeded.
Built-In-Test (BIT)
DYNAMIC
CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
+15 V
+5 V
±10%
+8 V
10mA max
Voltage Range
±5%
Max Voltage w/o Damage
+18 V
Current
25mA max
TEMPERATURE RANGES
Operating
-3XX
0° to +70°C
-1XX
-55° to +125°C
Storage
-65° to +150°C
2
LOGIC INPUT/OUTPUT
Logic outputs consist of 12 or 14 parallel data bits and CON-
VERTER BUSY (CB). All logic outputs are short-circuit proof to
ground and +5 volts. The CB output is a positive, 0.4 to 2 µs
pulse. Data changes about 50 ns after the leading edge of the
pulse because of an internal delay. Data is valid 0.2 µs after the
leading edge of CB. The angle is determined by the sum of the
bits at logic 1. Digital outputs are three-state and two bytes
wide; bits 1-8 (MSBs) are enabled by the signal EM, bits 9-14
(LSBs) are enable by the signal EL. Outputs are valid (logic 1
or 0) 150 ns max after setting EM or EL low and are high
impedance within 100 ns max of setting EM or EL high. Both
EM and EL are internally pulled-up to +5V at 30 µA max.
The inhibit (INH) input locks the transparent latch so the bits will
remain stable while data is being transferred (see FIGURE 1).
The output is stable 0.5 µs after INH is driven to logic 0 (see
FIGURE 3). A logic 0 at the T input latches the data, and a logic
1 applied to T will allow the bits to change. The inhibit transpar-
ent latch prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic 0 and the INH latch is transparent.
When CB goes to logic 1, the INH latch is locked. If CB occurs
after INH has been applied, the latch will remain locked and its
data will not change until CB returns to logic 0; if INH is applied
during CB, the latch will not lock until the CB pulse is over. The
purpose of the 50 ns delay is to prevent a race condition
between CB and INH where the up-down counter begins to
change as an INH is applied. Whenever an input angle change
occurs, the converter changes the digital angle in 1 LSB steps
and generates a converter busy pulse. Output data change is
initiated by the leading edge of the CB pulse, delayed by 50 ns,
nominal. Valid data is available at the outputs 0.2 µs after the
leading edge of CB, see FIGURE 4.
+V
S1-S3 = V
MAX
MAX
SINθ
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
-V
MAX
S3-S2 = V
S2-S1 = V
MAX
SIN(θ
+ 120°)
MAX
SIN(θ
+ 240°)
Standard Synchro Control Transmitter (CX) Outputs as a Function of
CCW Rotation From Electrical Zero (EZ)
+V
S2-S4 = V
MAX
MAX
COS
θ
In Phase with
RH-RL of Converter
and R2-R4 of RX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
-V
MAX
S1-S3 = V
MAX
SIN(θ)
Standard Resolver Control Transmitter (RX) Outputs as a Function of
CCW Rotation From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
ASYNCHROUS TO CB
INH
DIGITAL INTERFACE
The digital interface circuitry performs three main functions:
1. Latches the output bits during an Inhibit (INH) command
allowing stable data to be read out of the SDC-14532.
2. Furnishes parallel and tri-state data formats.
3. Acts as a buffer between the internal CMOS logic and the
external TTL logic.
Applying an inhibit command will lock the data in the transpar-
ent latch without interfering with the continuous tracking of the
feedback loop. Therefore, the digital angle is always updated,
and the inhibit can be applied for an arbitrary amount of time.
The inhibit transparent latch and the 50 ns delay are part of the
inhibit circuitry. The inhibit circuitry is described in detail the
logic input/output section.
DATA
FIGURE 3. INHIBIT TIMING DIAGRAM
,,
,,
0.5
µs
VALID
,,
,,
An INH input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer
asynchronous to CB is:
(1) Apply INH
(2) Wait 0.5 µs, min.
(3) Transfer the data.
(4) Release INH.
3
TABLE 2. DIGITAL ANGLE OUTPUTS
DYNAMIC PERFORMANCE
A Type II servo loop (Kv = 4) and very high acceleration con-
stants give the SDC-14532 superior dynamic performance, as
listed in TABLE 3. If the power supply voltages are not the +15V
DC nominal values, the specified input rates will increase or
decrease in proportion to the fractional change in voltage. A
Control Loop Block Diagram is show in FIGURE 6, and an Open
Loop Bode Plot is shown in FIGURE 7. The values of the trans-
fer function coefficients are shown in TABLE 3.
BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEG/BIT
180.0
90.0
45.0
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800.0
5400.0
2700.0
1350.0
675.0
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
2.75
ERROR PROCESSOR
INPUT
θ
+
-
CT
e
A
1
S + 1
B
S S +1
10B
VCO
A
2
S
VELOCITY
OUT
DIGITAL
POSITION
OUT
(φ)
Note: EM enables the MSBs and EL enables the LSBs.
H=1
6.1
µs
MIN
DEPENDS ON dφ/dt
CB
Open Loop Transfer function = Output
A
1
S + 1
2
B
S
2
S +1
10B
WHERE:
A
2
= A
1
A
2
0.2
µs
DATA
FIGURE 4. CONVERTER BUSY TIMING DIAGRAM
-1
2d
,
0.4-2.0
µs
VALID
,
FIGURE 6. CONTROL LOOP BLOCK DIAGRAM
Digital angle outputs are buffered and provided in a two-byte
format. The first byte always contains the MSBs (bits 1-8) and
is enabled by placing EM (pin 26) to logic 0. Depending on the
user-programmed resolution, the second byte will have bits 9
through 12 or 9 through 14, while operating at 12- or 14-bit res-
olution, respectively. Placing EL (pin 25) to logic 0 enables the
second byte (the LSBs). A logic 0 will be present on all the
unused least significant bits. TABLE 2 lists the deg/bit for the
digital angle outputs.
As long as the converter’s maximum tracking rate is not
exceeded there will be no velocity lag in the converter output,
although momentary acceleration errors remain. If a step input
occurs, as when the power is initially applied, the response will
be critically damped. FIGURE 5 shows the response to a step
input.
After initial slewing at the maximum tracking rate of the convert-
er there is one overshoot, which is inherent in a Type II servo.
The overshoot settling to a final value is a function of the small
signal settling time.
OVERSHOOT
θ
2
SETTLING TIME
GAIN = 4
2A
OPEN LOOP
B
A
ω
(rad/sec)
10B
FIGURE 7. OPEN LOOP BODE PLOT
TABLE 3. DYNAMIC CHARACTERISTICS
PARAMETER
Resolution
Input Frequency
Tracking Rate
Bandwidth
Ka
A1
A2
A
B
Settling Time
Bits
Hertz
RPS min
Hertz
1/sec
2
nom
1/sec nom
1/sec nom
1/sec nom
1/sec nom
ms max
UNITS
12
360-2600
48
135
90K
2.05
44K
300
150
90
14
360-2600
12
135
90K
2.05
44K
300
150
150
b/o
(CRITICALLY DAMPED)
(B = A/2)
ct
-6
db
/oc
t
GAIN = 0.4
θ
1
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
FIGURE 5. RESPONSE TO A STEP INPUT
4
TABLE 4. SDC-14532 PIN CONNECTION/FUNCTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION
1 (MSB)
2
3
4
5
6
7
8
9
10
11
12 (LSB 12-BIT MODE)
13
14 (LSB 14-BIT MODE)
RL
RH
PIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FUNCTION
S4 (Resolver Only)
S3
S2
S1
BIT
S
CASE
NC
EL (LSB enable)
EM (MSB enable)
CB (Converter Busy)
INH
+15V
GND
NC
+5V
1.155
(29.21)
0.900
(22.86)
16
17
0.180 MIN
(4.6)
0.210 MAX
(5.3)
1.755
(44.58)
15 EQ. SP.
0.100 = 1.500
TOL. NONCUM
(2.5 = 38)
1
32
0.12
(3.09)
BOTTOM
VIEW
0.120
(3.05)
0.018 ±0.002 (0.46 ±0.51)
DIA PIN 32 REQ'D
SIDE
VIEW
Notes:
1. Dimensions are in inches (millimeters).
2. Lead identification numbers are for reference only.
3. Lead spacing dimensions apply only at seating plane.
4. Pin material meets solderability requirements to MIL-STD-202E,
Method 208C
FIGURE 8. SDC-14532 MECHANICAL OUTLINE
5
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