EDI88130CS
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
s
Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
s
CS
1
, CS
2
& OE Functions for Bus Control
s
Inputs and Outputs Directly TTL Compatible
s
Organized as 128Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
Thru-hole and Surface Mount Packages JEDEC Pinout
•
•
•
•
•
•
32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)
32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)
32 lead Ceramic SOJ (Package 140)
32 pad Ceramic Quad LCC (Package 12)
32 pad Ceramic LCC (Package 141)
32 lead Ceramic Flatpack (Package 142)
The EDI88130CS is a high speed, high performance, 128Kx8 bits
monolithic Static RAM.
An additional chip enable line provides system memory security
during power down in non-battery backed up systems and memory
banking in high speed battery backed systems where large mul-
tiple pages of memory are required.
The EDI88130CS has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word.
A low power version, EDI88130LPS, offers a 2V data retention
function for battery back-up applications.
Military product is available compliant to MIL-PRF-38535.
* 15ns access time is advanced information, contact factory for availability.
s
Single +5V (±10%) Supply Operation
FIG. 1
PIN CONFIGURATION
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
32 QUAD LCC
PIN DESCRIPTION
I/O
0-7
A
0-16
WE
CS
1
, CS
2
29
28
27
26
25
24
23
22
21
TOP VIEW
A
12
A
14
A
16
NC
V
CC
A
15
CS
2
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V
±10%)
Ground
Not Connected
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 V
CC
31 A15
30 CS2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
4
3
2
1
32
31
30
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
1
I/O
7
OE
V
CC
V
SS
NC
BLOCK DIAGRAM
Memory Array
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
A
Ø-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE
CS
1
CS
2
OE
February 2000 Rev. 9
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88130CS
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Industrial
Military
Storage Temperature, Ceramic
Power Dissipation
Output Current
Junction Temperature, T
J
-0.2 to 7.0
-40 to +85
-55 to +125
-65 to +150
1.7
40
175
Unit
V
°C
°C
°C
W
mA
°C
OE
X
X
H
L
X
CS
1
H
X
L
L
L
CS
2
X
L
H
H
H
X
X
H
H
L
TRUTH TABLE
WE
Mode
Standby
Standby
Output Deselect
Read
Write
Output
High Z
High Z
High Z
Data Out
Data In
Power
Icc
2
, Icc
3
Icc
2
, Icc
3
Icc
1
Icc
1
Icc
1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C)
Max
Parameter
Address Lines
Data Lines
Symbol
C
I
C
O
Condition
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
LCC
6
8
CSOJ,DIP,
Unit
Flatpack
12
14
pF
pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5
Typ
5.0
0
—
—
Max
5.5
0
Vcc +0.5
+0.8
Unit
V
V
V
V
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Symbol
I
LI
I
LO
I
CC1
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE, CS
1
= V
IL
, I
I/O
= 0mA, CS
2
= V
IH
CS
1
≥
V
IH
and/or CS
2
≤
V
IL
,
V
IN
≥
V
IH
or
≤
V
IL
CS
1
≥
V
CC
-0.2V and/or CS
2
≤
0.2V
V
IN
≥
Vcc -0.2V or V
IN
≤
0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
(15-17ns)
(20ns)
(25-55ns)
(17-55ns)
(15ns)
CS (17-55ns)
CS (15ns)
LPS
Conditions
Min
—
—
—
—
—
—
—
—
—
—
—
2.4
Typ
—
—
Max
±5
±10
300
225
200
25
60
10
15
5
0.4
—
Units
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
Standby (TTL) Power Supply Current
I
CC2
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
I
CC3
V
OL
V
OH
3
—
—
—
—
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
3ns
1.5V
Figure 1
NOTE:
For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
Q
255Ω
30pF
Q
255Ω
5pF
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
EDI88130CS
AC CHARACTERISTICS – READ CYCLE (15 to 20ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
E1LQV
t
E2HQV
t
E1LQX
t
E2HQX
t
E1HQZ
t
E2LQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
E1LICCH
t
E2HICCH
t
E1HICCL
t
E2LICCL
t
RC
t
AA
t
ACS
t
ACS
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
t
PU
t
PU
t
PD
t
PD
0
0
15
15
0
5
0
0
17
17
3
6
0
6
0
0
20
20
5
5
6
6
3
6
0
8
15ns*
Min
15
15
15
15
5
5
7
7
3
7
Max
Min
17
17
17
17
5
5
8
8
17ns
Max
Min
20
20
20
20
20ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
* 15ns access time is advanced information, contact factory for availability.
AC CHARACTERISTICS – READ CYCLE (25 to 55ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
E1LQV
t
E2HQV
t
E1LQX
t
E2HQX
t
E1HQZ
t
E2LQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
E1LICCH
t
E2HICCH
t
E1HICCL
t
E2LICCL
t
RC
t
AA
t
ACS
t
ACS
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
t
PU
t
PU
t
PD
t
PD
0
0
25
25
0
10
0
0
35
35
0
10
0
15
0
0
45
45
5
5
10
10
0
15
0
20
0
0
55
55
25ns
Min
25
25
25
25
5
5
15
15
0
20
0
20
Max
Min
35
35
35
35
5
5
20
20
0
25
35ns
Max
Min
45
45
45
45
5
5
20
20
45ns
Max
Min
55
55
55
55
55ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88130CS
AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Parameter
Write Cycle Time
Chip Enable to End of Write
Symbol
JEDEC
t
AVAV
t
E1LWH
t
E1LE1H
t
E2HWH
t
E2HE2L
t
AVWL
t
AVE1L
t
AVE2H
t
AVWH
t
WLWH
t
WLE1H
t
WLE2L
t
WHAX
t
E1HAX
t
E2LAX
t
WHDX
t
E1HDX
t
E2LDX
t
WLQZ
t
DVWH
t
DVE1H
t
DVE2L
t
WHQX
15ns*
Alt.
t
WC
t
CW
t
CW
t
CW
t
CW
t
AS
t
AS
t
AS
t
AW
t
WP
t
WP
t
WP
t
WR
t
WR
t
WR
t
DH
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
DW
t
WLZ
Min
15
12
12
12
12
0
0
0
12
12
12
12
0
0
0
0
0
0
0
7
7
7
3
Max
Min
17
13
13
13
13
0
0
0
13
13
13
13
0
0
0
0
0
0
0
8
8
8
3
17ns
Max
Min
20
15
15
15
15
0
0
0
15
15
15
15
0
0
0
0
0
0
0
10
10
10
3
20ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
7
8
8
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0°C to +70°C)
Parameter
Write Cycle Time
Chip Enable to End of Write
Symbol
JEDEC
Alt.
t
AVAV
t
WC
t
E1LWH
t
CW
t
E1LE1H
t
CW
t
E2HWH
t
CW
t
E2HE2L
t
CW
t
AVWL
t
AS
t
AVE1L
t
AS
t
AVE2H
t
AS
t
AVWH
t
AW
t
AVEH
t
AW
t
WLWH
t
WP
t
WLE1H
t
WP
t
WLE2L
t
WP
t
WHAX
t
WR
t
E1HAX
t
WR
t
E2LAX
t
WR
t
WHDX
t
DH
t
E1HDX
t
DH
t
E2LDX
t
DH
t
WLQZ
t
WHZ
t
DVWH
t
DW
t
DW
t
DVE1H
t
DVE2L
t
DW
t
WHQX
t
WLZ
25ns
Min
25
20
16
16
0
0
0
20
20
20
20
20
0
0
0
0
0
0
0
15
15
15
3
0
0
0
25
25
30
30
30
0
0
0
0
0
0
0
20
20
20
3
Max
Min
35
25
20
20
0
0
0
35
35
30
30
30
5
5
5
0
0
0
0
20
20
20
3
35ns
Max
Min
45
35
25
25
0
0
0
45
45
35
35
35
5
5
5
0
0
0
0
25
25
25
3
45ns
Max
Min
55
45
40
40
55ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
20
25
40
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
10
13
15
20
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
EDI88130CS
FIG. 2
TIMING WAVEFORM - READ CYCLES
ADDRESS
t
AVAV
t
AVQV
CS
1
t
E1LQV
t
E1LQX
t
E1LICCH
t
E1HQZ
t
E1HICCL
t
E2LICCL
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
Icc
t
E2HQV
CS
2
t
E2HICCH
t
E2HQX
t
AVQV
DATA I/O
t
AVQX
DATA 1
DATA 2
OE
t
GLQV
t
GLQX
DATA I/O
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (CS
1
AND/OR CS
2
CONTROLLED, WE HIGH)
FIG. 3
WRITE CYCLE 1
ADDRESS
t
AVAV
t
AVWH
t
WLWH
t
AVWL
WE
t
WHAX
t
E1LWH
CS
1
CS
2
t
E2HWH
t
DVWH
t
WHDX
DATA IN
t
WLQZ
DATA OUT
t
WHQX
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
FIG. 4
ADDRESS
WRITE CYCLES 2
t
AVAV
WRITE CYCLES 3
t
AVAV
ADDRESS
t
AVE1L
WE
t
E1LE1H
t
E1HAX
WS32K32-XHX
t
t
AVE2H
E2HE2L
t
E2LAX
WE
CS
1
CS
1
CS
2
CS
2
t
DVE1H
DATA I/O
t
E1HDX
DATA I/O
t
DVE2L
t
E2LDX
WRITE CYCLE 2 - EARLY WRITE, CS
1
CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
5
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