SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Very Low Power Consumption . . .
5 mW Typ
Wide Driver Supply Voltage Range . . .
±4.5
V to
±15
V
Driver Output Slew Rate Limited to
30 V/µs Max
Receiver Input Hysteresis . . . 1000 mV Typ
Push-Pull Receiver Outputs
On-Chip Receiver 1-µs Noise Filter
Functionally Interchangeable With Motorola
MC145406 and Texas Instruments
TL145406
Package Options Include Plastic
Small-Outline (D, DW, NS) Packages and
DIPs (N)
SN65C1406 . . . D PACKAGE
SN75C1406 . . . D, DW, N, OR NS PACKAGE
(TOP VIEW)
V
DD
1RA
1DY
2RA
2DY
3RA
3DY
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
1RY
1DA
2RY
2DA
3RY
3DA
GND
description
The SN65C1406 and SN75C1406 are low-power BiMOS devices containing three independent drivers and
receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment
(DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1406
and SN75C1406 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver,
respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs, and the
receivers have filters that reject input noise pulses shorter than 1
µs.
Both these features eliminate the need
for external components.
The SN65C1406 and SN75C1406 are designed using low-power techniques in a BiMOS technology. In most
applications, the receivers contained in these devices interface to single inputs of peripheral devices such as
ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the
transition times of the input signals. If this is not the case, or for other uses, it is recommended that the
SN65C1406 and SN75C1406 receiver outputs be buffered by single Schmitt input gates or single gates of the
HCMOS, ALS, or 74F logic families.
The SN65C1406 is characterized for operation from –40°C to 85°C. The SN75C1406 is characterized for
operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL
OUTLINE
(D)
SN65C1406D
SN75C1406D
SMALL
OUTLINE
(DW)
—
SN75C1406DW
PLASTIC
DIP
(N)
—
SN75C1406N
PLASTIC
SMALL OUTLINE
(NS)
—
SN75C1406NS
–40°C to 85°C
0°C to 70°C
The D, DW, and PW packages are available taped and reeled. Add the suffix R to device type
(e.g., SN75C1406DR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
logic diagram (positive logic)
Typical of Each Receiver
RA
2, 4, 6
15, 13, 11
RY
Typical of Each Driver
3, 5, 7
14, 12, 10
DA
DY
2
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SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
schematics of inputs and outputs
EQUIVALENT DRIVER INPUT
EQUIVALENT DRIVER OUTPUT
VDD
VDD
Input
DA
Internal
1.4-V Reference
160
Ω
74
Ω
Output
DY
VSS
GND
72
Ω
VSS
EQUIVALENT RECEIVER INPUT
EQUIVALENT RECEIVER OUTPUT
VCC
Input
RA
3.4 kΩ
Output
RY
1.5 kΩ
ESD
Protection
ESD
Protection
530
Ω
GND
GND
All resistor values shown are nominal.
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SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage: V
DD
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, V
I
: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V
Output voltage range, V
O
: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
SS
– 6 V) to (V
DD
+ 6 V)
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
CC
+ 0.3 V)
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150
°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
VDD
VSS
VCC
VI
VIH
VIL
IOH
IOL
TA
Supply voltage
Supply voltage
Supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output curren
Operating free air temperature
free-air
SN65C1406
SN75C1406
–40
0
Driver
Receiver
2
0.8
–1
3.2
85
70
4.5
–4.5
4.5
VSS+ 2
NOM
12
–12
5
MAX
15
–15
6
VDD
±
25
UNIT
V
V
V
V
V
V
mA
mA
°C
4
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SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
DRIVER SECTION
electrical characteristics over operating free-air temperature range, V
DD
= 12 V, V
SS
= –12 V,
V
CC
= 5 V
±
10% (unless otherwise noted)
PARAMETER
VOH
VOL
IIH
IIL
IOS(H)
IOS(L)
IDD
ISS
rO
High-level
High level output voltage
Low-level output voltage
g
(see Note 3)
High-level input current
Low-level input current
High-level short-circuit
output current‡
Low-level short-circuit
output current‡
Supply current from VDD
Supply current from VSS
Output resistance
VIH = 0.8 V,
,
See Figure 1
VIH = 2 V,
,
See Figure 1
VI = 5 V,
VI = 0,
VI = 0.8 V,
VI = 2 V,
TEST CONDITIONS
RL = 3 kΩ,
RL = 3 kΩ,
See Figure 2
See Figure 2
VO = 0 or VSS,
VO = 0 or VDD,
See Figure 1
See Figure 1
VDD = 5 V,
VDD = 12 V,
VDD = 5 V,
VDD = 12 V,
VSS = – 5 V
VSS = – 12 V
VSS = – 5 V
VSS = – 12 V
300
–7.5
7.5
–12
12
115
115
–115
–115
400
VDD = 5 V,
VDD = 12 V,
VDD = 5 V,
VDD = 12 V,
VSS = – 5 V
VSS = – 12 V
VSS = – 5 V
VSS = – 12 V
MIN
4
10
TYP†
4.5
10.8
–4.4
–10.7
–4
–10
1
–1
–19.5
19.5
250
250
–250
–250
MAX
UNIT
V
V
µA
µA
mA
mA
µA
µA
Ω
No load,
,
All inputs at 2 V or 0.8 V
No load,
,
All inputs at 2 V or 0.8 V
VDD = VSS = VCC = 0,
See Note 4
VO = – 2 V to 2 V,
† All typical values are at TA = 25°C.
‡ Not more than one output should be shorted at a time.
NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
4. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics at T
A
= 25°C, V
DD
= 12 V, V
SS
= –12 V, V
CC
= 5 V
±
10%
PARAMETER
tPLH
tPHL
tTLH
tTHL
tTLH
tTHL
SR
Propagation delay time, low- to high-level output§
Propagation delay time, high- to low-level output§
Transition time, low- to high-level output¶
Transition time, high- to low-level output¶
Transition time, low- to high-level output#
Transition time, high- to low-level output#
Output slew rate
TEST CONDITIONS
RL = 3 kΩ to 7 kΩ, CL = 15 pF,
See Figure 3
RL = 3 kΩ to 7 kΩ, CL = 15 pF,
See Figure 3
RL = 3 kΩ to 7 kΩ, CL = 15 pF,
See Figure 3
RL = 3 kΩ to 7 kΩ, CL = 15 pF,
See Figure 3
RL = 3 kΩ to 7 kΩ, CL = 2500 pF,
See Figure 3
RL = 3 kΩ to 7 kΩ, CL = 2500 pF,
See Figure 3
RL = 3 kΩ to 7 kΩ, CL = 15 pF,
See Figure 3
4
0.53
0.53
MIN
TYP
1.2
2.5
2
2
1
1
10
MAX
3
3.5
3.2
3.2
2
2
30
UNIT
µs
µs
µs
µs
µs
µs
V/µs
§ tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points.
¶ Measured between 10% and 90% points of output waveform
# Measured between 3-V and – 3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low
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