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IDTCV107EPV8

产品描述Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小92KB,共21页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

IDTCV107EPV8概述

Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48

IDTCV107EPV8规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
零件包装代码SSOP
包装说明SSOP,
针数48
Reach Compliance Codecompliant
ECCN代码EAR99
JESD-30 代码R-PDSO-G48
JESD-609代码e0
长度15.875 mm
湿度敏感等级1
端子数量48
最高工作温度70 °C
最低工作温度
最大输出时钟频率200 MHz
封装主体材料PLASTIC/EPOXY
封装代码SSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度)225
主时钟/晶体标称频率14.31818 MHz
认证状态Not Qualified
座面最大高度2.794 mm
最大供电电压3.465 V
最小供电电压3.135 V
标称供电电压3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层TIN LEAD
端子形式GULL WING
端子节距0.635 mm
端子位置DUAL
处于峰值回流温度下的最长时间20
宽度7.493 mm
uPs/uCs/外围集成电路类型CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches1

文档预览

下载PDF文档
IDTCV107E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
IDTCV107E
FEATURES:
4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
IDTCV107E is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrum selection.
DESCRIPTION:
KEY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
EasyN
Programming
CPU CLK
Output Buffers
CPU[1:0]
X1
XTAL
Osc Amp
I
REF
REF 2.1.0
X2
PLL2
SSC
EasyN
Programming
SDATA
SCLK
SM Bus
Controller
AGP/PCI
Output Buffers
PCI[5:0], PCIF[2:0]
3V66[3:0]
PLL3
SSC
V
TT_PWRGD
Watch Dog
Timer
FS[1:0]
Control
Logic
SRC CLK
Output Buffer
SRC
I
REF
48MHz[1:0]
S
EL
24_48#
PLL4
48MHz
Output Buffer
24 - 48MHz
RESET#
OUTPUT TABLE
CPU (Pair)
2
3V66
3
3V66/VCH
1
PCI
6
PCIF
3
REF
3
48MHz
2
24 - 48MHz
1
SRC (Pair)
1
Reset#
1
COMMERCIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JANUARY 2004
DSC-6390/14

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