SN54LVTH125, SN74LVTH125
3.3 V ABT QUADRUPLE BUS BUFFERS
WITH 3 STATE OUTPUTS
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003
D
Support Mixed-Mode Signal Operation (5-V
D
D
D
Input and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
I
off
and Power-Up 3-State Support Hot
Insertion
D
Bus Hold on Data Inputs Eliminates the
D
D
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH125 . . . FK PACKAGE
(TOP VIEW)
1OE
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4OE
4A
4Y
3OE
3A
3Y
1
14
13
4OE
12
4A
11
4Y
10
3OE
9
3A
1A
1Y
2OE
2A
2Y
2
3
4
5
6
7
8
1Y
NC
2OE
NC
2A
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1A
1OE
NC
V
CC
4OE
4A
NC
4Y
NC
3OE
NC − No internal connection
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
LXH125
LVTH125
LVTH125
LXH125
LXH125
LXH125
SNJ54LVTH125J
SNJ54LVTH125W
SNJ54LVTH125FK
Copyright
2003, Texas Instruments Incorporated
GND
3Y
V
CC
SN54LVTH125 . . . J OR W PACKAGE
SN74LVTH125 . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
SN74LVTH125 . . . RGY PACKAGE
(TOP VIEW)
description/ordering information
These bus buffers are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the
high-impedance state when the associated output-enable (OE) input is high.
ORDERING INFORMATION
TA
PACKAGE†
QFN − RGY
SOIC − D
SOP − NS
−40°C to 85°C
SSOP − DB
TSSOP − PW
TVSOP − DGV
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Tape and reel
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
SN74LVTH125RGYR
SN74LVTH125D
SN74LVTH125DR
SN74LVTH125NSR
SN74LVTH125DBR
SN74LVTH125PW
SN74LVTH125PWR
SN74LVTH125DGVR
SNJ54LVTH125J
SNJ54LVTH125W
SNJ54LVTH125FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003
SN54LVTH125, SN74LVTH125
3.3 V ABT QUADRUPLE BUS BUFFERS
WITH 3 STATE OUTPUTS
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each buffer)
INPUTS
OE
L
L
H
A
H
L
X
OUTPUT
Y
H
L
Z
logic diagram (positive logic)
1OE
1A
1
2
3
3OE
1Y
3A
10
9
8
3Y
2OE
2A
4
5
6
4OE
2Y
4A
13
12
11
4Y
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54LVTH125, SN74LVTH125
3.3 V ABT QUADRUPLE BUS BUFFERS
WITH 3 STATE OUTPUTS
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, V
O
(see Note 1) . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Current into any output in the low state, I
O
: SN54LVTH125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I
O
(see Note 2): SN54LVTH125 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH125 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance,
θ
JA
(see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LVTH125
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
∆t/∆V
CC
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
Outputs enabled
200
−55
125
2.7
2
0.8
5.5
−24
48
10
200
−40
85
MAX
3.6
SN74LVTH125
MIN
2.7
2
0.8
5.5
−32
64
10
MAX
3.6
UNIT
V
V
V
V
mA
mA
ns/V
µs/V
°C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003
SN54LVTH125, SN74LVTH125
3.3 V ABT QUADRUPLE BUS BUFFERS
WITH 3 STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
VCC = 2.7 V,
VCC = 3 V
VCC = 2.7 V
VOL
VCC = 3 V
II = −18 mA
IOH = −100
µA
IOH = −8 mA
IOH = −24 mA
IOH = −32 mA
IOL = 100
µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = 5.5 V
VI = VCC or GND
VI = VCC
VI = 0
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VO = 3 V
VO = 0.5 V
75
−75
5
−5
±50∗
±50∗
0.12
4.5
0.12
0.19
7
0.19
0.3
4
6.5
4
6.5
0.12
4.5
0.12
SN54LVTH125
MIN
TYP†
MAX
−1.2
VCC−0.2
2.4
2
2
0.2
0.5
0.4
0.5
0.55
0.55
10
±1
1
−5
75
−75
±500
5
−5
±50
±50
0.19
7
0.19
0.2
mA
pF
pF
mA
µA
µA
µA
µA
µA
10
±1
1
−5
±100
µA
µA
0.2
0.5
0.4
0.5
V
VCC−0.2
2.4
V
SN74LVTH125
MIN
TYP†
MAX
−1.2
UNIT
V
VOH
VCC = 0 or 3.6 V,
II
Control
inputs
Data inputs
Ioff
II(hold)
IOZH
IOZL
IOZPU
IOZPD
Data inputs
VCC = 3.6 V,
VCC = 3.6 V
VCC = 0,
VCC = 3 V
VCC = 3.6 V‡,
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
Outputs high
Outputs low
Outputs disabled
ICC
∆I
CC§
Ci
Co
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0
VO = 3 V or 0
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54LVTH125, SN74LVTH125
3.3 V ABT QUADRUPLE BUS BUFFERS
WITH 3 STATE OUTPUTS
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH125
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.3 V
MIN
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1
A
OE
OE
Y
Y
Y
1
1
1.1
1.5
1.3
MAX
4.2
4.1
4.9
4.9
5.3
4.7
VCC = 2.7 V
MIN
MAX
4.7
5.1
5.6
5.6
5.9
4.2
SN74LVTH125
VCC = 3.3 V
±
0.3 V
MIN
1
1
1
1.1
1.5
1.3
TYP†
2
2.1
2
2.1
2.3
2.8
MAX
3.5
3.9
4
4
4.5
4.5
VCC = 2.7 V
MIN
MAX
4.5
4.9
5.5
5.4
5.7
4
ns
ns
ns
UNIT
† All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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