GS1532 HD-LINX™ II
Multi-Rate Serializer
GS1532 Data Sheet
Key Features
•
SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ
→
NRZI encoding (with
bypass)
DVB-ASI sync word insertion and 8b/10b encoding
user selectable additional processing features
including:
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•
•
•
•
•
•
•
•
•
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CRC, ANC data checksum, and line number
calculation and insertion
TRS and EDH packet generation and insertion
illegal code remapping
Description
The GS1532 is a multi-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1525 Voltage Controlled Oscillator, a transmit
solution can be realized for HD-SDI, SD-SDI and
DVB-ASI applications.
In addition to serializing the input, the GS1532 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats at both HD and SD
signal rates. An appropriate parallel clock input signal is
also required.
The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode, adjustable
signal swing, and automatic dual slew rate selection
depending on HD/SD operational requirements.
The GS1532 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
calculate and insert line numbers and CRC’s, re-map
illegal code words and insert SMPTE 352M payload
identifier packets. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.
The GS1532 is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant.
This component and all homogeneous subcomponents
are RoHS compliant.
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internal flywheel for noise immune TRS generation
20-bit / 10-bit CMOS parallel input data bus
148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital input
automatic standards detection and indication
Pb-free and RoHS Compliant
1.8V core power supply and 3.3V charge pump
power supply
3.3V digital I/O supply
JTAG test interface
small footprint compatible with GS1560A, GS1561,
GS9060, and GS9062
Applications
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SMPTE 292M Serial Digital Interfaces
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
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June 2005
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www.gennum.com
GS1532 Data Sheet
IOPROC_EN/DIS
SMPTE_BYPASS
DETECT_TRS
VCO_GND
dvb-asi
bypass
sd/hd
DIN[19:0]
I/O
Buffer
&
demux
20bit/10bit
JTAG/HOST
VCO_VCC
LB_CONT
DVB_ASI
LOCKED
CP_CAP
BLANK
HOST Interface /
JTAG test
SD/HD
CS_TMS
SCLK_TCK
PCLK
V
CO
VCO
LF
TRS insertion,
Line number
insertion,
CRC insertion,
data blank, code-
re-map and
flywheel
H
Reset
V
RESET_TRST
F
Phase detector, charge
pump, VCO control &
power supply
SDO_EN/DIS
DVB-ASI sync
word insert &
8b/10b encode
SMPTE
352M
generation
EDH
generation
& SMPTE
scramble
SDO
P -> S
SDO
RSET
SDIN_TDI
GS1532 Functional Block Diagram
21498 - 6
SDOUT_TDO
June 2005
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GS1532 Data Sheet
Contents
Key Features .................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics ........................................................................................14
2.1 Absolute Maximum Ratings ..........................................................................14
2.2 DC Electrical Characteristics ........................................................................14
2.3 AC Electrical Characteristics.........................................................................16
2.4 Solder Reflow Profiles...................................................................................18
2.5 Input/Output Circuits .....................................................................................19
2.6 Host Interface Maps......................................................................................21
2.6.1 Host Interface Map (Read Only Registers) .........................................22
2.6.2 Host Interface Map (R/W Configurable Registers) .............................23
3. Detailed Description ...............................................................................................24
3.1 Functional Overview .....................................................................................24
3.2 Parallel Data Inputs.......................................................................................24
3.2.1 Parallel Input in SMPTE Mode............................................................25
3.2.2 Parallel Input in DVB-ASI Mode..........................................................25
3.2.3 Parallel Input in Data-Through Mode ..................................................25
3.2.4 Parallel Input Clock (PCLK) ................................................................26
3.3 SMPTE Mode................................................................................................27
3.3.1 Internal Flywheel.................................................................................27
3.3.2 HVF Timing Signal Extraction .............................................................27
3.4 DVB-ASI mode..............................................................................................29
3.4.1 Control Signal Inputs ..........................................................................29
3.5 Data-Through Mode ......................................................................................29
3.6 Additional Processing Functions...................................................................30
3.6.1 Input Data Blank .................................................................................30
3.6.2 Automatic Video Standard Detection..................................................30
3.6.3 Packet Generation and Insertion ........................................................32
3.7 Parallel-To-Serial Conversion .......................................................................39
3.8 Serial Digital Data PLL..................................................................................40
3.8.1 External VCO......................................................................................40
3.8.2 Lock Detect Output .............................................................................40
3.9 Serial Digital Output ......................................................................................41
3.9.1 Output Swing ......................................................................................41
3.9.2 Serial Digital Output Mute...................................................................41
3.10 GSPI Host Interface ....................................................................................42
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June 2005
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GS1532 Data Sheet
3.10.1 Command Word Description.............................................................42
3.10.2 Data Read and Write Timing ............................................................43
3.10.3 Configuration and Status Registers ..................................................44
3.11 JTAG...........................................................................................................44
3.12 Device Power Up ........................................................................................46
3.13 Device Reset...............................................................................................46
4. Application Reference Design ................................................................................47
4.1 Typical Application Circuit .............................................................................47
5. References & Relevant Standards.........................................................................48
6. Package & Ordering Information............................................................................49
6.1 Package Dimensions ....................................................................................49
6.2 Packaging Data.............................................................................................50
6.3 Ordering Information .....................................................................................50
7. Revision History .....................................................................................................51
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June 2005
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GS1532 Data Sheet
1. Pin Out
1.1 Pin Assignment
IO_GND
IO_GND
IO_VDD
DIN16
DIN14
DIN13
DIN15
DIN12
IO_VDD
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18
19
20
DIN11
DIN17
DIN10
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
43
DIN2
42
60
59
58
57
56
55
54
53
52
51 50
49
48
47
46
45
44
IO_VDD
DIN18
DIN19
CORE_VDD
NC
NC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
IO_GND
DIN1
DIN0
CORE_VDD
H
V
F
CORE_GND
BLANK
NC
DETECT_TRS
CORE_GND
PCLK
NC
NC
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CS_TMS
JTAG/HOST
RESET_TRST
SDO
SDO
CD_GND
SDO_EN/DIS
LOCKED
VCO
VCO
VCO_GND
VCO_VCC
LF
CP_CAP
LB_CONT
CP_GND
NC
NC
NC
NC
PD_GND
NC
NC
NC
21498 - 6
June 2005
IOPROC_EN/DIS
SMPTE_BYPASS
20bit/10bit
DVB_ASI
CD_VDD
NC
RSV
NC
CP_VDD
PD_VDD
SD/HD
RSET
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